From 56340f4cd0a6ab318a52d2a62ded36aad2946e1d Mon Sep 17 00:00:00 2001 From: Amaury Pouly Date: Tue, 2 Aug 2016 15:18:41 +0100 Subject: hwstub: add the possibility to flush caches before exec This is needed on the jz4760b because if some data is loaded to DRAM, then it is cached and a disaster lurks if dcaches/icache are not flushed. Targets that needs this must define CONFIG_FLUSH_CACHES in target-config.h and implement target_flush_caches(). Currently MIPS has some generic code for mips32r1 that requires to define {D,I}CACHE_SIZE and {D,I}CACHE_LINE_SIZE in target-config.h Change-Id: I5a3fc085de9445d8c8a2eb61ae4e2dc9bb6b4e8e --- utils/hwstub/stub/jz4760b/target-config.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'utils/hwstub/stub/jz4760b/target-config.h') diff --git a/utils/hwstub/stub/jz4760b/target-config.h b/utils/hwstub/stub/jz4760b/target-config.h index fa018c14dc..681e17e6f6 100644 --- a/utils/hwstub/stub/jz4760b/target-config.h +++ b/utils/hwstub/stub/jz4760b/target-config.h @@ -3,6 +3,12 @@ #define TCSM0_SIZE 0x4000 #define CPU_MIPS #define STACK_SIZE 0x300 +#define DCACHE_SIZE 0x4000 /* 16 kB */ +#define DCACHE_LINE_SIZE 0x20 /* 32 B */ +#define ICACHE_SIZE 0x4000 /* 16 kB */ +#define ICACHE_LINE_SIZE 0x20 /* 32 B */ +/* we need to flush caches before executing */ +#define CONFIG_FLUSH_CACHES /* something provides define * #define mips 1 -- cgit v1.2.3