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author | Marcin Bukat <marcin.bukat@gmail.com> | 2014-09-23 13:30:17 +0200 |
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committer | Marcin Bukat <marcin.bukat@gmail.com> | 2014-11-05 08:18:59 +0100 |
commit | d11704fed5fd218b2ed26182de877bc6e5b513a4 (patch) | |
tree | 0eceaf96f006e9047b698ea99bf452faa79884d3 /utils/atj2137/adfuload/test_binary/backlight_c/crt0.S | |
parent | 791be56cff14a7a41774ce80ce401384291985d9 (diff) | |
download | rockbox-d11704fed5fd218b2ed26182de877bc6e5b513a4.tar.gz rockbox-d11704fed5fd218b2ed26182de877bc6e5b513a4.zip |
hwstub: Add atj213x supportbootloader_zenxfi3_v1
Change-Id: Ic32200f9ab2c6977e503307a9cbe43a1328d0341
Diffstat (limited to 'utils/atj2137/adfuload/test_binary/backlight_c/crt0.S')
-rw-r--r-- | utils/atj2137/adfuload/test_binary/backlight_c/crt0.S | 66 |
1 files changed, 42 insertions, 24 deletions
diff --git a/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S b/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S index 485a4fc26c..1d6293bd93 100644 --- a/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S +++ b/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S | |||
@@ -5,7 +5,7 @@ | |||
5 | 5 | ||
6 | .set mips32r2 | 6 | .set mips32r2 |
7 | .set noreorder | 7 | .set noreorder |
8 | .set noat | 8 | // .set noat |
9 | 9 | ||
10 | .section .init.text,"ax",%progbits | 10 | .section .init.text,"ax",%progbits |
11 | 11 | ||
@@ -18,50 +18,68 @@ load_addr: | |||
18 | addiu v0, ra, -12 # calc real load address | 18 | addiu v0, ra, -12 # calc real load address |
19 | # account for branch delay slot | 19 | # account for branch delay slot |
20 | # and very first 'di' instruction | 20 | # and very first 'di' instruction |
21 | la t0, relocstart | ||
22 | la t1, relocend | ||
23 | beq t0, v0, entry_point # no relocation needed | ||
24 | nop | ||
25 | 21 | ||
26 | reloc_loop: | ||
27 | lw t2, 0(v0) # src | ||
28 | addiu v0, 4 # inc src addr | ||
29 | addiu t0, 4 # inc dst addr | ||
30 | bne t0, t1, reloc_loop | ||
31 | sw t2, -4(t0) # dst | ||
32 | |||
33 | entry_point_jump: | ||
34 | la t0, entry_point | ||
35 | jr t0 | ||
36 | nop | ||
37 | |||
38 | entry_point: | ||
39 | # setup caches | 22 | # setup caches |
40 | # 4-way, 256 sets, 16 bytes cacheline I/D | 23 | # 4-way, 256 sets, 16 bytes cacheline I/D |
41 | li t0, 3 # enable cache for kseg0 accesses | ||
42 | mtc0 t0, C0_CONFIG | ||
43 | |||
44 | la t0, 0x80000000 # an idx op should use an unmappable address | 24 | la t0, 0x80000000 # an idx op should use an unmappable address |
45 | ori t1, t0, 0x4000 # 16kB cache | 25 | ori t1, t0, 0x4000 # 16kB cache |
46 | mtc0 zero, C0_TAGLO | 26 | mtc0 zero, C0_TAGLO |
47 | mtc0 zero, C0_TAGHI | 27 | mtc0 zero, C0_TAGHI |
28 | ehb # execution hazard barrier | ||
48 | 29 | ||
49 | cache_init_loop: | 30 | cache_init_loop: |
50 | cache 8, 0(t0) # index store icache tag | 31 | cache ICIndexStTag, 0(t0) # index store icache tag |
51 | cache 9, 0(t0) # index store dcache tag | 32 | cache DCIndexStTag, 0(t0) # index store dcache tag |
52 | addiu t0, t0, 0x10 | 33 | addiu t0, t0, 0x10 |
53 | bne t0, t1, cache_init_loop | 34 | bne t0, t1, cache_init_loop |
54 | nop | 35 | nop |
55 | 36 | ||
37 | li t0, 3 # enable cache for kseg0 accesses | ||
38 | mtc0 t0, C0_CONFIG | ||
39 | ehb | ||
40 | |||
41 | relocation: | ||
42 | la t0, relocstart | ||
43 | la t1, relocend | ||
44 | beq t0, v0, entry_point # no relocation needed | ||
45 | nop | ||
46 | |||
47 | reloc_loop: | ||
48 | lw s0, 0(v0) # src | ||
49 | lw s1, 4(v0) | ||
50 | lw s2, 8(v0) | ||
51 | lw s3, 12(v0) | ||
52 | |||
53 | sw s0, 0(t0) # dst | ||
54 | sw s1, 4(t0) | ||
55 | sw s2, 8(t0) | ||
56 | sw s3, 12(t0) | ||
57 | |||
58 | synci 0(t0) # dcache writeback invalidate | ||
59 | # icache invalidate | ||
60 | |||
61 | addiu t0, t0, 16 # inc dst addr | ||
62 | blt t0, t1, reloc_loop | ||
63 | addiu v0, v0, 16 # inc src addr | ||
64 | |||
65 | entry_point_jump: | ||
66 | la t0, entry_point | ||
67 | jr.hb t0 # jump register with hazard barier | ||
68 | nop | ||
69 | |||
70 | entry_point: | ||
56 | # clear bss | 71 | # clear bss |
57 | la t0, bssbegin | 72 | la t0, bssbegin |
58 | la t1, bssend | 73 | la t1, bssend |
59 | 74 | beq t0, t1, stack_setup | |
75 | nop | ||
76 | |||
60 | clear_bss_loop: | 77 | clear_bss_loop: |
61 | addiu t0, 4 | 78 | addiu t0, 4 |
62 | bne t0, t1, clear_bss_loop | 79 | bne t0, t1, clear_bss_loop |
63 | sw zero, -4(t0) | 80 | sw zero, -4(t0) |
64 | 81 | ||
82 | stack_setup: | ||
65 | # setup stack | 83 | # setup stack |
66 | la sp, stackend | 84 | la sp, stackend |
67 | la t0, stackbegin | 85 | la t0, stackbegin |