From d11704fed5fd218b2ed26182de877bc6e5b513a4 Mon Sep 17 00:00:00 2001
From: Marcin Bukat <marcin.bukat@gmail.com>
Date: Tue, 23 Sep 2014 13:30:17 +0200
Subject: hwstub: Add atj213x support

Change-Id: Ic32200f9ab2c6977e503307a9cbe43a1328d0341
---
 .../adfuload/test_binary/backlight_c/crt0.S        | 66 ++++++++++++++--------
 1 file changed, 42 insertions(+), 24 deletions(-)

(limited to 'utils/atj2137/adfuload/test_binary/backlight_c/crt0.S')

diff --git a/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S b/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S
index 485a4fc26c..1d6293bd93 100644
--- a/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S
+++ b/utils/atj2137/adfuload/test_binary/backlight_c/crt0.S
@@ -5,7 +5,7 @@
 
     .set mips32r2
     .set noreorder
-    .set noat
+//    .set noat
 
     .section .init.text,"ax",%progbits
 
@@ -18,50 +18,68 @@ load_addr:
     addiu v0, ra, -12          # calc real load address
                                # account for branch delay slot
                                # and very first 'di' instruction
-    la t0, relocstart
-    la t1, relocend
-    beq t0, v0, entry_point    # no relocation needed
-    nop
 
-reloc_loop:
-    lw t2, 0(v0)               # src
-    addiu v0, 4                # inc src addr
-    addiu t0, 4                # inc dst addr
-    bne t0, t1, reloc_loop
-    sw t2, -4(t0)              # dst
-
-entry_point_jump:
-    la t0, entry_point
-    jr t0
-    nop
-
-entry_point:
     # setup caches
     # 4-way, 256 sets, 16 bytes cacheline I/D
-    li      t0, 3              # enable cache for kseg0 accesses
-    mtc0    t0, C0_CONFIG
-
     la      t0, 0x80000000     # an idx op should use an unmappable address
     ori     t1, t0, 0x4000     # 16kB cache
     mtc0    zero, C0_TAGLO
     mtc0    zero, C0_TAGHI
+    ehb                        # execution hazard barrier
 
 cache_init_loop:
-    cache   8, 0(t0)           # index store icache tag
-    cache   9, 0(t0)           # index store dcache tag
+    cache   ICIndexStTag, 0(t0)           # index store icache tag
+    cache   DCIndexStTag, 0(t0)           # index store dcache tag
     addiu   t0, t0, 0x10
     bne     t0, t1, cache_init_loop
     nop
 
+    li      t0, 3              # enable cache for kseg0 accesses
+    mtc0    t0, C0_CONFIG
+    ehb
+
+relocation:
+    la t0, relocstart
+    la t1, relocend
+    beq t0, v0, entry_point    # no relocation needed
+    nop
+
+reloc_loop:
+    lw s0, 0(v0)               # src
+    lw s1, 4(v0)
+    lw s2, 8(v0)
+    lw s3, 12(v0)
+
+    sw s0, 0(t0)               # dst
+    sw s1, 4(t0)
+    sw s2, 8(t0)
+    sw s3, 12(t0)
+
+    synci 0(t0)                # dcache writeback invalidate
+                               # icache invalidate
+
+    addiu t0, t0, 16           # inc dst addr
+    blt t0, t1, reloc_loop
+    addiu v0, v0, 16           # inc src addr
+
+entry_point_jump:
+    la t0, entry_point
+    jr.hb t0                   # jump register with hazard barier
+    nop
+
+entry_point:
     # clear bss
     la t0, bssbegin
     la t1, bssend
-
+    beq t0, t1, stack_setup
+    nop
+    
 clear_bss_loop:
     addiu t0, 4
     bne t0, t1, clear_bss_loop
     sw zero, -4(t0)
 
+stack_setup:
     # setup stack
     la sp, stackend
     la t0, stackbegin
-- 
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