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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-07-27 19:01:40 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-07-27 19:01:40 +0000 |
commit | d0a132a7a4fa358489180e511a6f594eee3e0fb2 (patch) | |
tree | ea37a14c93bfaf16de5741b1b08c021824f7ad16 /firmware | |
parent | e38f3abac90b1fd10c22a0769e66d724f53502ad (diff) | |
download | rockbox-d0a132a7a4fa358489180e511a6f594eee3e0fb2.tar.gz rockbox-d0a132a7a4fa358489180e511a6f594eee3e0fb2.zip |
Jz4740 timer driver: only init timer in timer_set() when start is true
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22075 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/timer-jz4740.c | 31 |
1 files changed, 19 insertions, 12 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c index c174ca6eb1..5bc030eeb2 100644 --- a/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/timer-jz4740.c | |||
@@ -46,17 +46,6 @@ bool timer_set(long cycles, bool start) | |||
46 | pfn_unregister = NULL; | 46 | pfn_unregister = NULL; |
47 | } | 47 | } |
48 | 48 | ||
49 | old_irq = disable_irq_save(); | ||
50 | |||
51 | __tcu_stop_counter(1); | ||
52 | __tcu_disable_pwm_output(1); | ||
53 | |||
54 | __tcu_mask_half_match_irq(1); | ||
55 | __tcu_unmask_full_match_irq(1); | ||
56 | |||
57 | /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */ | ||
58 | __tcu_select_extalclk(1); | ||
59 | |||
60 | /* Increase prescale values starting from 0 to make the cycle count fit */ | 49 | /* Increase prescale values starting from 0 to make the cycle count fit */ |
61 | while(divider > 65535 && prescaler <= 1024) | 50 | while(divider > 65535 && prescaler <= 1024) |
62 | { | 51 | { |
@@ -65,6 +54,20 @@ bool timer_set(long cycles, bool start) | |||
65 | divider = cycles / prescaler; | 54 | divider = cycles / prescaler; |
66 | } | 55 | } |
67 | 56 | ||
57 | old_irq = disable_irq_save(); | ||
58 | |||
59 | __tcu_stop_counter(1); | ||
60 | if(start) | ||
61 | { | ||
62 | __tcu_disable_pwm_output(1); | ||
63 | |||
64 | __tcu_mask_half_match_irq(1); | ||
65 | __tcu_unmask_full_match_irq(1); | ||
66 | |||
67 | /* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */ | ||
68 | __tcu_select_extalclk(1); | ||
69 | } | ||
70 | |||
68 | REG_TCU_TCSR(1) = (REG_TCU_TCSR(1) & ~TCU_TCSR_PRESCALE_MASK) | (prescaler_bit << TCU_TCSR_PRESCALE_BIT); | 71 | REG_TCU_TCSR(1) = (REG_TCU_TCSR(1) & ~TCU_TCSR_PRESCALE_MASK) | (prescaler_bit << TCU_TCSR_PRESCALE_BIT); |
69 | REG_TCU_TCNT(1) = 0; | 72 | REG_TCU_TCNT(1) = 0; |
70 | REG_TCU_TDHR(1) = 0; | 73 | REG_TCU_TDHR(1) = 0; |
@@ -72,7 +75,11 @@ bool timer_set(long cycles, bool start) | |||
72 | 75 | ||
73 | __tcu_clear_full_match_flag(1); | 76 | __tcu_clear_full_match_flag(1); |
74 | 77 | ||
75 | system_enable_irq(IRQ_TCU1); | 78 | if(start) |
79 | { | ||
80 | system_enable_irq(IRQ_TCU1); | ||
81 | __tcu_start_counter(1); | ||
82 | } | ||
76 | 83 | ||
77 | restore_irq(old_irq); | 84 | restore_irq(old_irq); |
78 | 85 | ||