diff options
author | Michael Sparmann <theseven@rockbox.org> | 2009-10-20 06:37:07 +0000 |
---|---|---|
committer | Michael Sparmann <theseven@rockbox.org> | 2009-10-20 06:37:07 +0000 |
commit | d03fe64dcf80633c7ec78f122682e78fb59fe2d8 (patch) | |
tree | a404d7fccf244445572f92b796fb5433c3523d58 /firmware | |
parent | 3ad3bec0ad6d8bada7e70d6f646b4b13a2fedbf4 (diff) | |
download | rockbox-d03fe64dcf80633c7ec78f122682e78fb59fe2d8.tar.gz rockbox-d03fe64dcf80633c7ec78f122682e78fb59fe2d8.zip |
iPod Nano 2G USB support based on the S3C6400X datasheet. Disabled by default for now.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23285 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/SOURCES | 2 | ||||
-rw-r--r-- | firmware/export/config-ipodnano2g.h | 12 | ||||
-rw-r--r-- | firmware/export/usb-s3c6400x.h | 341 | ||||
-rw-r--r-- | firmware/target/arm/s5l8700/usb-s5l8700.c | 56 | ||||
-rw-r--r-- | firmware/target/arm/usb-s3c6400x.c | 429 | ||||
-rw-r--r-- | firmware/usb.c | 4 | ||||
-rw-r--r-- | firmware/usbstack/usb_storage.c | 6 |
7 files changed, 790 insertions, 60 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index b91d49b7f7..a3c47a6ddb 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -1326,6 +1326,7 @@ target/arm/s5l8700/udacodec-meizu.c | |||
1326 | #ifdef IPOD_NANO2G | 1326 | #ifdef IPOD_NANO2G |
1327 | #ifndef SIMULATOR | 1327 | #ifndef SIMULATOR |
1328 | drivers/audio/wm8975.c | 1328 | drivers/audio/wm8975.c |
1329 | target/arm/usb-s3c6400x.c | ||
1329 | target/arm/ipod/button-clickwheel.c | 1330 | target/arm/ipod/button-clickwheel.c |
1330 | target/arm/s5l8700/kernel-s5l8700.c | 1331 | target/arm/s5l8700/kernel-s5l8700.c |
1331 | target/arm/s5l8700/wmcodec-s5l8700.c | 1332 | target/arm/s5l8700/wmcodec-s5l8700.c |
@@ -1333,7 +1334,6 @@ target/arm/s5l8700/pcm-s5l8700.c | |||
1333 | target/arm/s5l8700/adc-s5l8700.c | 1334 | target/arm/s5l8700/adc-s5l8700.c |
1334 | target/arm/s5l8700/debug-s5l8700.c | 1335 | target/arm/s5l8700/debug-s5l8700.c |
1335 | target/arm/s5l8700/dma-s5l8700.c | 1336 | target/arm/s5l8700/dma-s5l8700.c |
1336 | target/arm/s5l8700/usb-s5l8700.c | ||
1337 | target/arm/s5l8700/ipodnano2g/backlight-nano2g.c | 1337 | target/arm/s5l8700/ipodnano2g/backlight-nano2g.c |
1338 | target/arm/s5l8700/ipodnano2g/lcd-nano2g.c | 1338 | target/arm/s5l8700/ipodnano2g/lcd-nano2g.c |
1339 | target/arm/s5l8700/ipodnano2g/powermgmt-nano2g.c | 1339 | target/arm/s5l8700/ipodnano2g/powermgmt-nano2g.c |
diff --git a/firmware/export/config-ipodnano2g.h b/firmware/export/config-ipodnano2g.h index 25e9eff3f0..0946610eac 100644 --- a/firmware/export/config-ipodnano2g.h +++ b/firmware/export/config-ipodnano2g.h | |||
@@ -161,9 +161,6 @@ | |||
161 | /* USB On-the-go */ | 161 | /* USB On-the-go */ |
162 | //#define CONFIG_USBOTG USBOTG_M5636 | 162 | //#define CONFIG_USBOTG USBOTG_M5636 |
163 | 163 | ||
164 | /* We reboot into the OF to handle USB */ | ||
165 | #define USB_HANDLED_BY_OF | ||
166 | |||
167 | /* Define this if you can read an absolute wheel position */ | 164 | /* Define this if you can read an absolute wheel position */ |
168 | #define HAVE_WHEEL_POSITION | 165 | #define HAVE_WHEEL_POSITION |
169 | 166 | ||
@@ -201,3 +198,12 @@ | |||
201 | #define MIN_BRIGHTNESS_SETTING 1 | 198 | #define MIN_BRIGHTNESS_SETTING 1 |
202 | #define MAX_BRIGHTNESS_SETTING 0x2e | 199 | #define MAX_BRIGHTNESS_SETTING 0x2e |
203 | #define DEFAULT_BRIGHTNESS_SETTING 0x20 | 200 | #define DEFAULT_BRIGHTNESS_SETTING 0x20 |
201 | |||
202 | /* USB defines */ | ||
203 | #define HAVE_USBSTACK | ||
204 | #define USB_ENABLE_STORAGE | ||
205 | #define USB_VENDOR_ID 0x05AC | ||
206 | #define USB_PRODUCT_ID 0x1260 | ||
207 | #define USB_NUM_ENDPOINTS 5 | ||
208 | /* #define USE_ROCKBOX_USB - needs testing */ | ||
209 | #define USB_DEVBSS_ATTR __attribute__((aligned(16))) | ||
diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h new file mode 100644 index 0000000000..22b0769681 --- /dev/null +++ b/firmware/export/usb-s3c6400x.h | |||
@@ -0,0 +1,341 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2009 Michael Sparmann | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef USB_S3C6400X_H | ||
22 | #define USB_S3C6400X_H | ||
23 | |||
24 | |||
25 | #define REG32_PTR_T volatile uint32_t * | ||
26 | |||
27 | |||
28 | /*** OTG PHY CONTROL REGISTERS ***/ | ||
29 | #define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000) | ||
30 | #define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004) | ||
31 | #define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008) | ||
32 | |||
33 | /*** OTG LINK CORE REGISTERS ***/ | ||
34 | /* Core Global Registers */ | ||
35 | #define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000) | ||
36 | #define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004) | ||
37 | #define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008) | ||
38 | #define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C) | ||
39 | #define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010) | ||
40 | #define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014) | ||
41 | #define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018) | ||
42 | #define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C) | ||
43 | #define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020) | ||
44 | #define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024) | ||
45 | #define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028) | ||
46 | #define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C) | ||
47 | #define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100) | ||
48 | #define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x) | ||
49 | #define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104) | ||
50 | #define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108) | ||
51 | #define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C) | ||
52 | #define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110) | ||
53 | #define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114) | ||
54 | #define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118) | ||
55 | #define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C) | ||
56 | #define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120) | ||
57 | #define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124) | ||
58 | #define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128) | ||
59 | #define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C) | ||
60 | #define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130) | ||
61 | #define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134) | ||
62 | #define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138) | ||
63 | #define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C) | ||
64 | |||
65 | /*** HOST MODE REGISTERS ***/ | ||
66 | /* Host Global Registers */ | ||
67 | #define HCFG *(REG32_PTR_T)(OTGBASE + 0x400) | ||
68 | #define HFIR *(REG32_PTR_T)(OTGBASE + 0x404) | ||
69 | #define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408) | ||
70 | #define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410) | ||
71 | #define HAINT *(REG32_PTR_T)(OTGBASE + 0x414) | ||
72 | #define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418) | ||
73 | |||
74 | /* Host Port Control and Status Registers */ | ||
75 | #define HPRT *(REG32_PTR_T)(OTGBASE + 0x440) | ||
76 | |||
77 | /* Host Channel-Specific Registers */ | ||
78 | #define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x) | ||
79 | #define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x) | ||
80 | #define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x) | ||
81 | #define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x) | ||
82 | #define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x) | ||
83 | #define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x) | ||
84 | #define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500) | ||
85 | #define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504) | ||
86 | #define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508) | ||
87 | #define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C) | ||
88 | #define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510) | ||
89 | #define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514) | ||
90 | #define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520) | ||
91 | #define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524) | ||
92 | #define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528) | ||
93 | #define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C) | ||
94 | #define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530) | ||
95 | #define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534) | ||
96 | #define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540) | ||
97 | #define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544) | ||
98 | #define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548) | ||
99 | #define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C) | ||
100 | #define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550) | ||
101 | #define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554) | ||
102 | #define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560) | ||
103 | #define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564) | ||
104 | #define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568) | ||
105 | #define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C) | ||
106 | #define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570) | ||
107 | #define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574) | ||
108 | #define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580) | ||
109 | #define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584) | ||
110 | #define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588) | ||
111 | #define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C) | ||
112 | #define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590) | ||
113 | #define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594) | ||
114 | #define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0) | ||
115 | #define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4) | ||
116 | #define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8) | ||
117 | #define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC) | ||
118 | #define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0) | ||
119 | #define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4) | ||
120 | #define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0) | ||
121 | #define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4) | ||
122 | #define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8) | ||
123 | #define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC) | ||
124 | #define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0) | ||
125 | #define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4) | ||
126 | #define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0) | ||
127 | #define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4) | ||
128 | #define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8) | ||
129 | #define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC) | ||
130 | #define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0) | ||
131 | #define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4) | ||
132 | #define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600) | ||
133 | #define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604) | ||
134 | #define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608) | ||
135 | #define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C) | ||
136 | #define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610) | ||
137 | #define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614) | ||
138 | #define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620) | ||
139 | #define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624) | ||
140 | #define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628) | ||
141 | #define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C) | ||
142 | #define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630) | ||
143 | #define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634) | ||
144 | #define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640) | ||
145 | #define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644) | ||
146 | #define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648) | ||
147 | #define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C) | ||
148 | #define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650) | ||
149 | #define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654) | ||
150 | #define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660) | ||
151 | #define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664) | ||
152 | #define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668) | ||
153 | #define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C) | ||
154 | #define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670) | ||
155 | #define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674) | ||
156 | #define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680) | ||
157 | #define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684) | ||
158 | #define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688) | ||
159 | #define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C) | ||
160 | #define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690) | ||
161 | #define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694) | ||
162 | #define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0) | ||
163 | #define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4) | ||
164 | #define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8) | ||
165 | #define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC) | ||
166 | #define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0) | ||
167 | #define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4) | ||
168 | #define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0) | ||
169 | #define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4) | ||
170 | #define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8) | ||
171 | #define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC) | ||
172 | #define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0) | ||
173 | #define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4) | ||
174 | #define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0) | ||
175 | #define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4) | ||
176 | #define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8) | ||
177 | #define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC) | ||
178 | #define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0) | ||
179 | #define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4) | ||
180 | |||
181 | /*** DEVICE MODE REGISTERS ***/ | ||
182 | /* Device Global Registers */ | ||
183 | #define DCFG *(REG32_PTR_T)(OTGBASE + 0x800) | ||
184 | #define DCTL *(REG32_PTR_T)(OTGBASE + 0x804) | ||
185 | #define DSTS *(REG32_PTR_T)(OTGBASE + 0x808) | ||
186 | #define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810) | ||
187 | #define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814) | ||
188 | #define DAINT *(REG32_PTR_T)(OTGBASE + 0x818) | ||
189 | #define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C) | ||
190 | #define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820) | ||
191 | #define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824) | ||
192 | #define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828) | ||
193 | #define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C) | ||
194 | #define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830) | ||
195 | #define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834) | ||
196 | |||
197 | /* Device Logical IN Endpoint-Specific Registers */ | ||
198 | #define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x) | ||
199 | #define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x) | ||
200 | #define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x) | ||
201 | #define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x) | ||
202 | #define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900) | ||
203 | #define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908) | ||
204 | #define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910) | ||
205 | #define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914) | ||
206 | #define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920) | ||
207 | #define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928) | ||
208 | #define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930) | ||
209 | #define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934) | ||
210 | #define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940) | ||
211 | #define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948) | ||
212 | #define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950) | ||
213 | #define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954) | ||
214 | #define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960) | ||
215 | #define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968) | ||
216 | #define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970) | ||
217 | #define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974) | ||
218 | #define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980) | ||
219 | #define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988) | ||
220 | #define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990) | ||
221 | #define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994) | ||
222 | #define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0) | ||
223 | #define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8) | ||
224 | #define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0) | ||
225 | #define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4) | ||
226 | #define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0) | ||
227 | #define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8) | ||
228 | #define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0) | ||
229 | #define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4) | ||
230 | #define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0) | ||
231 | #define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8) | ||
232 | #define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0) | ||
233 | #define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4) | ||
234 | #define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00) | ||
235 | #define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08) | ||
236 | #define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10) | ||
237 | #define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14) | ||
238 | #define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20) | ||
239 | #define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28) | ||
240 | #define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30) | ||
241 | #define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34) | ||
242 | #define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40) | ||
243 | #define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48) | ||
244 | #define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50) | ||
245 | #define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54) | ||
246 | #define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60) | ||
247 | #define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68) | ||
248 | #define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70) | ||
249 | #define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74) | ||
250 | #define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80) | ||
251 | #define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88) | ||
252 | #define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90) | ||
253 | #define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94) | ||
254 | #define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0) | ||
255 | #define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8) | ||
256 | #define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0) | ||
257 | #define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4) | ||
258 | #define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0) | ||
259 | #define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8) | ||
260 | #define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0) | ||
261 | #define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4) | ||
262 | #define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0) | ||
263 | #define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8) | ||
264 | #define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0) | ||
265 | #define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4) | ||
266 | |||
267 | /* Device Logical OUT Endpoint-Specific Registers */ | ||
268 | #define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x) | ||
269 | #define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x) | ||
270 | #define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x) | ||
271 | #define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x) | ||
272 | #define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00) | ||
273 | #define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08) | ||
274 | #define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10) | ||
275 | #define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14) | ||
276 | #define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20) | ||
277 | #define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28) | ||
278 | #define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30) | ||
279 | #define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34) | ||
280 | #define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40) | ||
281 | #define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48) | ||
282 | #define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50) | ||
283 | #define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54) | ||
284 | #define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60) | ||
285 | #define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68) | ||
286 | #define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70) | ||
287 | #define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74) | ||
288 | #define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80) | ||
289 | #define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88) | ||
290 | #define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90) | ||
291 | #define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94) | ||
292 | #define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0) | ||
293 | #define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8) | ||
294 | #define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0) | ||
295 | #define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4) | ||
296 | #define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0) | ||
297 | #define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8) | ||
298 | #define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0) | ||
299 | #define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4) | ||
300 | #define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0) | ||
301 | #define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8) | ||
302 | #define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0) | ||
303 | #define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4) | ||
304 | #define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00) | ||
305 | #define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08) | ||
306 | #define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10) | ||
307 | #define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14) | ||
308 | #define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20) | ||
309 | #define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28) | ||
310 | #define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30) | ||
311 | #define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34) | ||
312 | #define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40) | ||
313 | #define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48) | ||
314 | #define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50) | ||
315 | #define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54) | ||
316 | #define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60) | ||
317 | #define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68) | ||
318 | #define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70) | ||
319 | #define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74) | ||
320 | #define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80) | ||
321 | #define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88) | ||
322 | #define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90) | ||
323 | #define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94) | ||
324 | #define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0) | ||
325 | #define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8) | ||
326 | #define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0) | ||
327 | #define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4) | ||
328 | #define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0) | ||
329 | #define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8) | ||
330 | #define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0) | ||
331 | #define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4) | ||
332 | #define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0) | ||
333 | #define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8) | ||
334 | #define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0) | ||
335 | #define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4) | ||
336 | |||
337 | /* Power and Clock Gating Register */ | ||
338 | #define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00) | ||
339 | |||
340 | |||
341 | #endif /* USB_S3C6400X_H */ | ||
diff --git a/firmware/target/arm/s5l8700/usb-s5l8700.c b/firmware/target/arm/s5l8700/usb-s5l8700.c deleted file mode 100644 index c0bf7a951b..0000000000 --- a/firmware/target/arm/s5l8700/usb-s5l8700.c +++ /dev/null | |||
@@ -1,56 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id: usb-fw-pp502x.c 21932 2009-07-17 22:07:06Z roolku $ | ||
9 | * | ||
10 | * Copyright (C) 2009 by ????? | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #include "config.h" | ||
22 | #include "usb.h" | ||
23 | #include "cpu.h" | ||
24 | #include "system.h" | ||
25 | #include "string.h" | ||
26 | |||
27 | void usb_init_device(void) | ||
28 | { | ||
29 | } | ||
30 | |||
31 | void usb_enable(bool on) | ||
32 | { | ||
33 | /* This device specific code will eventually give way to proper USB | ||
34 | handling, which should be the same for all S5L870x targets. */ | ||
35 | if (on) | ||
36 | { | ||
37 | #ifdef IPOD_ARCH | ||
38 | /* For iPod, we can only do one thing with USB mode atm - reboot | ||
39 | into the flash-based disk-mode. This does not return. */ | ||
40 | |||
41 | memcpy((void *)0x0002bf00, "diskmodehotstuff\1\0\0\0", 20); | ||
42 | |||
43 | system_reboot(); /* Reboot */ | ||
44 | #endif | ||
45 | } | ||
46 | } | ||
47 | |||
48 | int usb_detect(void) | ||
49 | { | ||
50 | #if defined(IPOD_NANO2G) | ||
51 | if ((PDAT14 & 0x8) == 0x0) | ||
52 | return USB_INSERTED; | ||
53 | #endif | ||
54 | |||
55 | return USB_EXTRACTED; | ||
56 | } | ||
diff --git a/firmware/target/arm/usb-s3c6400x.c b/firmware/target/arm/usb-s3c6400x.c new file mode 100644 index 0000000000..3034cf8029 --- /dev/null +++ b/firmware/target/arm/usb-s3c6400x.c | |||
@@ -0,0 +1,429 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2009 by Michael Sparmann | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "usb.h" | ||
24 | |||
25 | #define OTGBASE 0x38800000 | ||
26 | #define PHYBASE 0x3C400000 | ||
27 | #include "usb-s3c6400x.h" | ||
28 | |||
29 | #include "cpu.h" | ||
30 | #include "system.h" | ||
31 | #include "kernel.h" | ||
32 | #include "panic.h" | ||
33 | |||
34 | #ifdef HAVE_USBSTACK | ||
35 | #include "usb_ch9.h" | ||
36 | #include "usb_core.h" | ||
37 | #include <inttypes.h> | ||
38 | #include "sprintf.h" | ||
39 | #include "power.h" | ||
40 | |||
41 | struct ep_type | ||
42 | { | ||
43 | bool active; | ||
44 | bool busy; | ||
45 | bool done; | ||
46 | int rc; | ||
47 | int size; | ||
48 | struct wakeup complete; | ||
49 | } ; | ||
50 | |||
51 | static struct ep_type endpoints[5]; | ||
52 | static struct usb_ctrlrequest ctrlreq USB_DEVBSS_ATTR; | ||
53 | |||
54 | int usb_drv_port_speed(void) | ||
55 | { | ||
56 | return (DSTS & 2) == 0 ? 1 : 0; | ||
57 | } | ||
58 | |||
59 | void reset_endpoints(int reinit) | ||
60 | { | ||
61 | unsigned int i; | ||
62 | for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++) | ||
63 | { | ||
64 | if (reinit) endpoints[i].active = false; | ||
65 | endpoints[i].busy = false; | ||
66 | endpoints[i].rc = -1; | ||
67 | endpoints[i].done = true; | ||
68 | wakeup_signal(&endpoints[i].complete); | ||
69 | } | ||
70 | DIEPCTL0 = 0x8800; /* EP0 IN ACTIVE NEXT=1 */ | ||
71 | DOEPCTL0 = 0x8000; /* EP0 OUT ACTIVE */ | ||
72 | DOEPTSIZ0 = 0x20080040; /* EP0 OUT Transfer Size: | ||
73 | 64 Bytes, 1 Packet, 1 Setup Packet */ | ||
74 | DOEPDMA0 = (uint32_t)&ctrlreq; | ||
75 | DOEPCTL0 |= 0x84000000; /* EP0 OUT ENABLE CLEARNAK */ | ||
76 | if (reinit) | ||
77 | { | ||
78 | /* The size is getting set to zero, because we don't know | ||
79 | whether we are Full Speed or High Speed at this stage */ | ||
80 | /* EP1 IN INACTIVE DATA0 SIZE=0 NEXT=3 */ | ||
81 | DIEPCTL1 = 0x10001800; | ||
82 | /* EP2 OUT INACTIVE DATA0 SIZE=0 */ | ||
83 | DOEPCTL2 = 0x10000000; | ||
84 | /* EP3 IN INACTIVE DATA0 SIZE=0 NEXT=0 */ | ||
85 | DIEPCTL3 = 0x10000000; | ||
86 | /* EP4 OUT INACTIVE DATA0 SIZE=0 */ | ||
87 | DOEPCTL4 = 0x10000000; | ||
88 | } | ||
89 | else | ||
90 | { | ||
91 | /* INACTIVE DATA0 */ | ||
92 | DIEPCTL1 = (DIEPCTL1 & ~0x00008000) | 0x10000000; | ||
93 | DOEPCTL2 = (DOEPCTL2 & ~0x00008000) | 0x10000000; | ||
94 | DIEPCTL3 = (DIEPCTL3 & ~0x00008000) | 0x10000000; | ||
95 | DOEPCTL4 = (DOEPCTL4 & ~0x00008000) | 0x10000000; | ||
96 | } | ||
97 | DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */ | ||
98 | } | ||
99 | |||
100 | int usb_drv_request_endpoint(int type, int dir) | ||
101 | { | ||
102 | size_t ep; | ||
103 | int ret = -1; | ||
104 | |||
105 | if (dir == USB_DIR_IN) ep = 1; | ||
106 | else ep = 2; | ||
107 | |||
108 | while (ep < 5) | ||
109 | { | ||
110 | if (!endpoints[ep].active) | ||
111 | { | ||
112 | endpoints[ep].active = true; | ||
113 | ret = ep | dir; | ||
114 | uint32_t newbits = (type << 18) | 0x10000000; | ||
115 | if (dir) DIEPCTL(ep) = (DIEPCTL(ep) & ~0x000C0000) | newbits; | ||
116 | else DOEPCTL(ep) = (DOEPCTL(ep) & ~0x000C0000) | newbits; | ||
117 | break; | ||
118 | } | ||
119 | ep += 2; | ||
120 | } | ||
121 | |||
122 | return ret; | ||
123 | } | ||
124 | |||
125 | void usb_drv_release_endpoint(int ep) | ||
126 | { | ||
127 | ep = ep & 0x7f; | ||
128 | |||
129 | if (ep < 1 || ep > USB_NUM_ENDPOINTS) return; | ||
130 | |||
131 | endpoints[ep].active = false; | ||
132 | } | ||
133 | |||
134 | static void usb_reset(void) | ||
135 | { | ||
136 | volatile int i; | ||
137 | |||
138 | DCTL = 0x802; /* Soft Disconnect */ | ||
139 | |||
140 | OPHYPWR = 0; /* PHY: Power up */ | ||
141 | ORSTCON = 1; /* PHY: Assert Software Reset */ | ||
142 | for (i = 0; i < 50; i++); | ||
143 | ORSTCON = 0; /* PHY: Deassert Software Reset */ | ||
144 | OPHYCLK = 0; /* PHY: 48MHz clock */ | ||
145 | |||
146 | GRSTCTL = 1; /* OTG: Assert Software Reset */ | ||
147 | while (GRSTCTL & 1); /* Wait for OTG to ack reset */ | ||
148 | while (!(GRSTCTL & 0x80000000)); /* Wait for OTG AHB master idle */ | ||
149 | |||
150 | GAHBCFG = 0x27; /* OTG AHB config: Unmask ints, burst length 4, DMA on */ | ||
151 | GUSBCFG = 0x1408; /* OTG: 16bit PHY and some reserved bits */ | ||
152 | |||
153 | DCFG = 4; /* Address 0 */ | ||
154 | DCTL = 0x800; /* Soft Reconnect */ | ||
155 | DIEPMSK = 0x0D; /* IN EP interrupt mask */ | ||
156 | DOEPMSK = 0x0D; /* IN EP interrupt mask */ | ||
157 | GINTMSK = 0xC3000; /* Interrupt mask: IN event, OUT event, bus reset */ | ||
158 | |||
159 | reset_endpoints(1); | ||
160 | } | ||
161 | |||
162 | /* IRQ handler */ | ||
163 | void INT_USB_FUNC(void) | ||
164 | { | ||
165 | int i; | ||
166 | if (GINTSTS & 0x1000) /* bus reset */ | ||
167 | { | ||
168 | DCFG = 4; /* Address 0 */ | ||
169 | reset_endpoints(1); | ||
170 | usb_core_bus_reset(); | ||
171 | } | ||
172 | |||
173 | if (GINTSTS & 0x2000) /* enumeration done, we now know the speed */ | ||
174 | { | ||
175 | /* Set up the maximum packet sizes accordingly */ | ||
176 | uint32_t maxpacket = usb_drv_port_speed() ? 512 : 64; | ||
177 | DIEPCTL1 = (DIEPCTL1 & ~0x000003FF) | maxpacket; | ||
178 | DOEPCTL2 = (DOEPCTL2 & ~0x000003FF) | maxpacket; | ||
179 | DIEPCTL3 = (DIEPCTL3 & ~0x000003FF) | maxpacket; | ||
180 | DOEPCTL4 = (DOEPCTL4 & ~0x000003FF) | maxpacket; | ||
181 | } | ||
182 | |||
183 | if (GINTSTS & 0x40000) /* IN EP event */ | ||
184 | for (i = 0; i < 5; i ++) | ||
185 | if (i != 2 && i != 4 && DIEPINT(i)) | ||
186 | { | ||
187 | if (DIEPINT(i) & 1) /* Transfer completed */ | ||
188 | { | ||
189 | invalidate_dcache(); | ||
190 | int bytes = endpoints[i].size - (DIEPTSIZ(i) & 0x3FFFF); | ||
191 | if (endpoints[i].busy) | ||
192 | { | ||
193 | endpoints[i].busy = false; | ||
194 | endpoints[i].rc = 0; | ||
195 | endpoints[i].done = true; | ||
196 | usb_core_transfer_complete(i, USB_DIR_IN, 0, bytes); | ||
197 | wakeup_signal(&endpoints[i].complete); | ||
198 | } | ||
199 | } | ||
200 | if (DIEPINT(i) & 4) /* AHB error */ | ||
201 | panicf("USB: AHB error on IN EP%d", i); | ||
202 | if (DIEPINT(i) & 8) /* Timeout */ | ||
203 | { | ||
204 | if (endpoints[i].busy) | ||
205 | { | ||
206 | endpoints[i].busy = false; | ||
207 | endpoints[i].rc = 1; | ||
208 | endpoints[i].done = true; | ||
209 | wakeup_signal(&endpoints[i].complete); | ||
210 | } | ||
211 | } | ||
212 | DIEPINT(i) = DIEPINT(i); | ||
213 | } | ||
214 | |||
215 | if (GINTSTS & 0x80000) /* OUT EP event */ | ||
216 | for (i = 0; i < 5; i += 2) | ||
217 | if (DOEPINT(i)) | ||
218 | { | ||
219 | if (DOEPINT(i) & 1) /* Transfer completed */ | ||
220 | { | ||
221 | invalidate_dcache(); | ||
222 | int bytes = endpoints[i].size - (DOEPTSIZ(i) & 0x3FFFF); | ||
223 | if (endpoints[i].busy) | ||
224 | { | ||
225 | endpoints[i].busy = false; | ||
226 | endpoints[i].rc = 0; | ||
227 | endpoints[i].done = true; | ||
228 | usb_core_transfer_complete(i, USB_DIR_OUT, 0, bytes); | ||
229 | wakeup_signal(&endpoints[i].complete); | ||
230 | } | ||
231 | } | ||
232 | if (DOEPINT(i) & 4) /* AHB error */ | ||
233 | panicf("USB: AHB error on OUT EP%d", i); | ||
234 | if (DOEPINT(i) & 8) /* SETUP phase done */ | ||
235 | { | ||
236 | invalidate_dcache(); | ||
237 | if (i == 0) | ||
238 | { | ||
239 | if (ctrlreq.bRequest == 5) | ||
240 | { | ||
241 | /* Already set the new address here, | ||
242 | before passing the packet to the core. | ||
243 | See below (usb_drv_set_address) for details. */ | ||
244 | DCFG = (DCFG & ~0x7F0) | (ctrlreq.wValue << 4); | ||
245 | } | ||
246 | usb_core_control_request(&ctrlreq); | ||
247 | } | ||
248 | else panicf("USB: SETUP done on OUT EP%d!?", i); | ||
249 | } | ||
250 | /* Make sure EP0 OUT is set up to accept the next request */ | ||
251 | if (!i) | ||
252 | { | ||
253 | DOEPTSIZ0 = 0x20080040; | ||
254 | DOEPDMA0 = (uint32_t)&ctrlreq; | ||
255 | DOEPCTL0 |= 0x84000000; | ||
256 | } | ||
257 | DOEPINT(i) = DOEPINT(i); | ||
258 | } | ||
259 | |||
260 | GINTSTS = GINTSTS; | ||
261 | } | ||
262 | |||
263 | void usb_drv_set_address(int address) | ||
264 | { | ||
265 | (void)address; | ||
266 | /* Ignored intentionally, because the controller requires us to set the | ||
267 | new address before sending the response for some reason. So we'll | ||
268 | already set it when the control request arrives, before passing that | ||
269 | into the USB core, which will then call this dummy function. */ | ||
270 | } | ||
271 | |||
272 | void ep_send(int ep, void *ptr, int length) | ||
273 | { | ||
274 | endpoints[ep].busy = true; | ||
275 | endpoints[ep].size = length; | ||
276 | DIEPCTL(ep) |= 0x8000; /* EPx OUT ACTIVE */ | ||
277 | int blocksize = usb_drv_port_speed() ? 512 : 64; | ||
278 | int packets = (length + blocksize - 1) / blocksize; | ||
279 | if (!length) DIEPTSIZ(ep) = 1 << 19; /* one empty packet */ | ||
280 | else DIEPTSIZ(ep) = length | (packets << 19); | ||
281 | DIEPDMA(ep) = (uint32_t)ptr; | ||
282 | clean_dcache(); | ||
283 | DIEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */ | ||
284 | } | ||
285 | |||
286 | void ep_recv(int ep, void *ptr, int length) | ||
287 | { | ||
288 | endpoints[ep].busy = true; | ||
289 | endpoints[ep].size = length; | ||
290 | DOEPCTL(ep) &= ~0x20000; /* EPx UNSTALL */ | ||
291 | DOEPCTL(ep) |= 0x8000; /* EPx OUT ACTIVE */ | ||
292 | int blocksize = usb_drv_port_speed() ? 512 : 64; | ||
293 | int packets = (length + blocksize - 1) / blocksize; | ||
294 | if (!length) DIEPTSIZ(ep) = 1 << 19; /* one empty packet */ | ||
295 | else DOEPTSIZ(ep) = length | (packets << 19); | ||
296 | DOEPDMA(ep) = (uint32_t)ptr; | ||
297 | clean_dcache(); | ||
298 | DOEPCTL(ep) |= 0x84000000; /* EPx OUT ENABLE CLEARNAK */ | ||
299 | } | ||
300 | |||
301 | int usb_drv_send(int endpoint, void *ptr, int length) | ||
302 | { | ||
303 | endpoint &= 0x7f; | ||
304 | endpoints[endpoint].done = false; | ||
305 | ep_send(endpoint, ptr, length); | ||
306 | while (!endpoints[endpoint].done && endpoints[endpoint].busy) | ||
307 | wakeup_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK); | ||
308 | return endpoints[endpoint].rc; | ||
309 | } | ||
310 | |||
311 | int usb_drv_send_nonblocking(int endpoint, void *ptr, int length) | ||
312 | { | ||
313 | ep_send(endpoint & 0x7f, ptr, length); | ||
314 | return 0; | ||
315 | } | ||
316 | |||
317 | int usb_drv_recv(int endpoint, void* ptr, int length) | ||
318 | { | ||
319 | ep_recv(endpoint & 0x7f, ptr, length); | ||
320 | return 0; | ||
321 | } | ||
322 | |||
323 | void usb_drv_cancel_all_transfers(void) | ||
324 | { | ||
325 | int flags = disable_irq_save(); | ||
326 | reset_endpoints(0); | ||
327 | restore_irq(flags); | ||
328 | } | ||
329 | |||
330 | void usb_drv_set_test_mode(int mode) | ||
331 | { | ||
332 | (void)mode; | ||
333 | } | ||
334 | |||
335 | bool usb_drv_stalled(int endpoint, bool in) | ||
336 | { | ||
337 | if (in) return DIEPCTL(endpoint) & 0x00200000 ? true : false; | ||
338 | else return DOEPCTL(endpoint) & 0x00200000 ? true : false; | ||
339 | } | ||
340 | |||
341 | void usb_drv_stall(int endpoint, bool stall, bool in) | ||
342 | { | ||
343 | if (in) | ||
344 | { | ||
345 | if (stall) DIEPCTL(endpoint) |= 0x00200000; | ||
346 | else DIEPCTL(endpoint) &= ~0x00200000; | ||
347 | } | ||
348 | else | ||
349 | { | ||
350 | if (stall) DOEPCTL(endpoint) |= 0x00200000; | ||
351 | else DOEPCTL(endpoint) &= ~0x00200000; | ||
352 | } | ||
353 | } | ||
354 | |||
355 | void usb_drv_init(void) | ||
356 | { | ||
357 | /* Enable USB clock */ | ||
358 | PWRCON &= ~0x4000; | ||
359 | PWRCONEXT &= ~0x800; | ||
360 | PCGCCTL = 0; | ||
361 | |||
362 | /* unmask irq */ | ||
363 | INTMSK |= INTMSK_USB_OTG; | ||
364 | |||
365 | /* reset the beast */ | ||
366 | usb_reset(); | ||
367 | } | ||
368 | |||
369 | void usb_drv_exit(void) | ||
370 | { | ||
371 | DCTL = 0x802; /* Soft Disconnect */ | ||
372 | |||
373 | OPHYPWR = 0xF; /* PHY: Power down */ | ||
374 | |||
375 | PCGCCTL = 1; /* Mask clocks */ | ||
376 | PWRCON |= 0x4000; | ||
377 | PWRCONEXT |= 0x800; | ||
378 | } | ||
379 | |||
380 | void usb_init_device(void) | ||
381 | { | ||
382 | unsigned int i; | ||
383 | for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++) | ||
384 | wakeup_init(&endpoints[i].complete); | ||
385 | usb_drv_exit(); | ||
386 | } | ||
387 | |||
388 | void usb_enable(bool on) | ||
389 | { | ||
390 | if (on) usb_core_init(); | ||
391 | else usb_core_exit(); | ||
392 | } | ||
393 | |||
394 | void usb_attach(void) | ||
395 | { | ||
396 | usb_enable(true); | ||
397 | } | ||
398 | |||
399 | int usb_detect(void) | ||
400 | { | ||
401 | if (charger_inserted()) | ||
402 | return USB_INSERTED; | ||
403 | return USB_EXTRACTED; | ||
404 | } | ||
405 | |||
406 | #else | ||
407 | void usb_init_device(void) | ||
408 | { | ||
409 | /* simply switch USB off for now */ | ||
410 | DCTL = 0x802; /* Soft Disconnect */ | ||
411 | |||
412 | OPHYPWR = 0xF; /* PHY: Power down */ | ||
413 | |||
414 | PCGCCTL = 1; /* Mask clocks */ | ||
415 | PWRCON |= 0x4000; | ||
416 | PWRCONEXT |= 0x800; | ||
417 | } | ||
418 | |||
419 | void usb_enable(bool on) | ||
420 | { | ||
421 | (void)on; | ||
422 | } | ||
423 | |||
424 | /* Always return false for now */ | ||
425 | int usb_detect(void) | ||
426 | { | ||
427 | return USB_EXTRACTED; | ||
428 | } | ||
429 | #endif | ||
diff --git a/firmware/usb.c b/firmware/usb.c index ea07a8447d..bac1258d50 100644 --- a/firmware/usb.c +++ b/firmware/usb.c | |||
@@ -109,6 +109,10 @@ static void try_reboot(void) | |||
109 | #endif /* CONFIG_CPU */ | 109 | #endif /* CONFIG_CPU */ |
110 | #endif /* IPOD_ARCH */ | 110 | #endif /* IPOD_ARCH */ |
111 | 111 | ||
112 | #ifdef IPOD_NANO2G | ||
113 | memcpy((void *)0x0002bf00, "diskmodehotstuff\1\0\0\0", 20); | ||
114 | #endif | ||
115 | |||
112 | system_reboot(); /* Reboot */ | 116 | system_reboot(); /* Reboot */ |
113 | } | 117 | } |
114 | #endif /* USB_FIRWIRE_HANDLING || (HAVE_USBSTACK && !USE_ROCKBOX_USB) */ | 118 | #endif /* USB_FIRWIRE_HANDLING || (HAVE_USBSTACK && !USE_ROCKBOX_USB) */ |
diff --git a/firmware/usbstack/usb_storage.c b/firmware/usbstack/usb_storage.c index d16277a5f1..88a669b64a 100644 --- a/firmware/usbstack/usb_storage.c +++ b/firmware/usbstack/usb_storage.c | |||
@@ -44,7 +44,9 @@ | |||
44 | #define RAMDISK_SIZE 2048 | 44 | #define RAMDISK_SIZE 2048 |
45 | #endif | 45 | #endif |
46 | 46 | ||
47 | #ifndef SECTOR_SIZE | ||
47 | #define SECTOR_SIZE 512 | 48 | #define SECTOR_SIZE 512 |
49 | #endif | ||
48 | 50 | ||
49 | /* the ARC driver currently supports up to 64k USB transfers. This is | 51 | /* the ARC driver currently supports up to 64k USB transfers. This is |
50 | * enough for efficient mass storage support, as commonly host OSes | 52 | * enough for efficient mass storage support, as commonly host OSes |
@@ -454,7 +456,11 @@ void usb_storage_init_connection(void) | |||
454 | unsigned char * audio_buffer; | 456 | unsigned char * audio_buffer; |
455 | 457 | ||
456 | audio_buffer = audio_get_buffer(false,&bufsize); | 458 | audio_buffer = audio_get_buffer(false,&bufsize); |
459 | #ifdef UNCACHED_ADDR | ||
457 | cbw_buffer = (void *)UNCACHED_ADDR((unsigned int)(audio_buffer+31) & 0xffffffe0); | 460 | cbw_buffer = (void *)UNCACHED_ADDR((unsigned int)(audio_buffer+31) & 0xffffffe0); |
461 | #else | ||
462 | cbw_buffer = (void *)((unsigned int)(audio_buffer+31) & 0xffffffe0); | ||
463 | #endif | ||
458 | tb.transfer_buffer = cbw_buffer + 1024; | 464 | tb.transfer_buffer = cbw_buffer + 1024; |
459 | cpucache_invalidate(); | 465 | cpucache_invalidate(); |
460 | #ifdef USB_USE_RAMDISK | 466 | #ifdef USB_USE_RAMDISK |