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diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h
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1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 Michael Sparmann
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef USB_S3C6400X_H
22#define USB_S3C6400X_H
23
24
25#define REG32_PTR_T volatile uint32_t *
26
27
28/*** OTG PHY CONTROL REGISTERS ***/
29#define OPHYPWR *(REG32_PTR_T)(PHYBASE + 0x000)
30#define OPHYCLK *(REG32_PTR_T)(PHYBASE + 0x004)
31#define ORSTCON *(REG32_PTR_T)(PHYBASE + 0x008)
32
33/*** OTG LINK CORE REGISTERS ***/
34/* Core Global Registers */
35#define GOTGCTL *(REG32_PTR_T)(OTGBASE + 0x000)
36#define GOTGINT *(REG32_PTR_T)(OTGBASE + 0x004)
37#define GAHBCFG *(REG32_PTR_T)(OTGBASE + 0x008)
38#define GUSBCFG *(REG32_PTR_T)(OTGBASE + 0x00C)
39#define GRSTCTL *(REG32_PTR_T)(OTGBASE + 0x010)
40#define GINTSTS *(REG32_PTR_T)(OTGBASE + 0x014)
41#define GINTMSK *(REG32_PTR_T)(OTGBASE + 0x018)
42#define GRXSTSR *(REG32_PTR_T)(OTGBASE + 0x01C)
43#define GRXSTSP *(REG32_PTR_T)(OTGBASE + 0x020)
44#define GRXFSIZ *(REG32_PTR_T)(OTGBASE + 0x024)
45#define GNPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x028)
46#define GNPTXSTS *(REG32_PTR_T)(OTGBASE + 0x02C)
47#define HPTXFSIZ *(REG32_PTR_T)(OTGBASE + 0x100)
48#define DPTXFSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x100 + 4 * x)
49#define DPTXFSIZ1 *(REG32_PTR_T)(OTGBASE + 0x104)
50#define DPTXFSIZ2 *(REG32_PTR_T)(OTGBASE + 0x108)
51#define DPTXFSIZ3 *(REG32_PTR_T)(OTGBASE + 0x10C)
52#define DPTXFSIZ4 *(REG32_PTR_T)(OTGBASE + 0x110)
53#define DPTXFSIZ5 *(REG32_PTR_T)(OTGBASE + 0x114)
54#define DPTXFSIZ6 *(REG32_PTR_T)(OTGBASE + 0x118)
55#define DPTXFSIZ7 *(REG32_PTR_T)(OTGBASE + 0x11C)
56#define DPTXFSIZ8 *(REG32_PTR_T)(OTGBASE + 0x120)
57#define DPTXFSIZ9 *(REG32_PTR_T)(OTGBASE + 0x124)
58#define DPTXFSIZ10 *(REG32_PTR_T)(OTGBASE + 0x128)
59#define DPTXFSIZ11 *(REG32_PTR_T)(OTGBASE + 0x12C)
60#define DPTXFSIZ12 *(REG32_PTR_T)(OTGBASE + 0x130)
61#define DPTXFSIZ13 *(REG32_PTR_T)(OTGBASE + 0x134)
62#define DPTXFSIZ14 *(REG32_PTR_T)(OTGBASE + 0x138)
63#define DPTXFSIZ15 *(REG32_PTR_T)(OTGBASE + 0x13C)
64
65/*** HOST MODE REGISTERS ***/
66/* Host Global Registers */
67#define HCFG *(REG32_PTR_T)(OTGBASE + 0x400)
68#define HFIR *(REG32_PTR_T)(OTGBASE + 0x404)
69#define HFNUM *(REG32_PTR_T)(OTGBASE + 0x408)
70#define HPTXSTS *(REG32_PTR_T)(OTGBASE + 0x410)
71#define HAINT *(REG32_PTR_T)(OTGBASE + 0x414)
72#define HAINTMSK *(REG32_PTR_T)(OTGBASE + 0x418)
73
74/* Host Port Control and Status Registers */
75#define HPRT *(REG32_PTR_T)(OTGBASE + 0x440)
76
77/* Host Channel-Specific Registers */
78#define HCCHAR(x) *(REG32_PTR_T)(OTGBASE + 0x500 + 0x20 * x)
79#define HCSPLT(x) *(REG32_PTR_T)(OTGBASE + 0x504 + 0x20 * x)
80#define HCINT(x) *(REG32_PTR_T)(OTGBASE + 0x508 + 0x20 * x)
81#define HCINTMSK(x) *(REG32_PTR_T)(OTGBASE + 0x50C + 0x20 * x)
82#define HCTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x510 + 0x20 * x)
83#define HCDMA(x) *(REG32_PTR_T)(OTGBASE + 0x514 + 0x20 * x)
84#define HCCHAR0 *(REG32_PTR_T)(OTGBASE + 0x500)
85#define HCSPLT0 *(REG32_PTR_T)(OTGBASE + 0x504)
86#define HCINT0 *(REG32_PTR_T)(OTGBASE + 0x508)
87#define HCINTMSK0 *(REG32_PTR_T)(OTGBASE + 0x50C)
88#define HCTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x510)
89#define HCDMA0 *(REG32_PTR_T)(OTGBASE + 0x514)
90#define HCCHAR1 *(REG32_PTR_T)(OTGBASE + 0x520)
91#define HCSPLT1 *(REG32_PTR_T)(OTGBASE + 0x524)
92#define HCINT1 *(REG32_PTR_T)(OTGBASE + 0x528)
93#define HCINTMSK1 *(REG32_PTR_T)(OTGBASE + 0x52C)
94#define HCTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x530)
95#define HCDMA1 *(REG32_PTR_T)(OTGBASE + 0x534)
96#define HCCHAR2 *(REG32_PTR_T)(OTGBASE + 0x540)
97#define HCSPLT2 *(REG32_PTR_T)(OTGBASE + 0x544)
98#define HCINT2 *(REG32_PTR_T)(OTGBASE + 0x548)
99#define HCINTMSK2 *(REG32_PTR_T)(OTGBASE + 0x54C)
100#define HCTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x550)
101#define HCDMA2 *(REG32_PTR_T)(OTGBASE + 0x554)
102#define HCCHAR3 *(REG32_PTR_T)(OTGBASE + 0x560)
103#define HCSPLT3 *(REG32_PTR_T)(OTGBASE + 0x564)
104#define HCINT3 *(REG32_PTR_T)(OTGBASE + 0x568)
105#define HCINTMSK3 *(REG32_PTR_T)(OTGBASE + 0x56C)
106#define HCTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x570)
107#define HCDMA3 *(REG32_PTR_T)(OTGBASE + 0x574)
108#define HCCHAR4 *(REG32_PTR_T)(OTGBASE + 0x580)
109#define HCSPLT4 *(REG32_PTR_T)(OTGBASE + 0x584)
110#define HCINT4 *(REG32_PTR_T)(OTGBASE + 0x588)
111#define HCINTMSK4 *(REG32_PTR_T)(OTGBASE + 0x58C)
112#define HCTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x590)
113#define HCDMA4 *(REG32_PTR_T)(OTGBASE + 0x594)
114#define HCCHAR5 *(REG32_PTR_T)(OTGBASE + 0x5A0)
115#define HCSPLT5 *(REG32_PTR_T)(OTGBASE + 0x5A4)
116#define HCINT5 *(REG32_PTR_T)(OTGBASE + 0x5A8)
117#define HCINTMSK5 *(REG32_PTR_T)(OTGBASE + 0x5AC)
118#define HCTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x5B0)
119#define HCDMA5 *(REG32_PTR_T)(OTGBASE + 0x5B4)
120#define HCCHAR6 *(REG32_PTR_T)(OTGBASE + 0x5C0)
121#define HCSPLT6 *(REG32_PTR_T)(OTGBASE + 0x5C4)
122#define HCINT6 *(REG32_PTR_T)(OTGBASE + 0x5C8)
123#define HCINTMSK6 *(REG32_PTR_T)(OTGBASE + 0x5CC)
124#define HCTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x5D0)
125#define HCDMA6 *(REG32_PTR_T)(OTGBASE + 0x5D4)
126#define HCCHAR7 *(REG32_PTR_T)(OTGBASE + 0x5E0)
127#define HCSPLT7 *(REG32_PTR_T)(OTGBASE + 0x5E4)
128#define HCINT7 *(REG32_PTR_T)(OTGBASE + 0x5E8)
129#define HCINTMSK7 *(REG32_PTR_T)(OTGBASE + 0x5EC)
130#define HCTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x5F0)
131#define HCDMA7 *(REG32_PTR_T)(OTGBASE + 0x5F4)
132#define HCCHAR8 *(REG32_PTR_T)(OTGBASE + 0x600)
133#define HCSPLT8 *(REG32_PTR_T)(OTGBASE + 0x604)
134#define HCINT8 *(REG32_PTR_T)(OTGBASE + 0x608)
135#define HCINTMSK8 *(REG32_PTR_T)(OTGBASE + 0x60C)
136#define HCTSIZ8 *(REG32_PTR_T)(OTGBASE + 0x610)
137#define HCDMA8 *(REG32_PTR_T)(OTGBASE + 0x614)
138#define HCCHAR9 *(REG32_PTR_T)(OTGBASE + 0x620)
139#define HCSPLT9 *(REG32_PTR_T)(OTGBASE + 0x624)
140#define HCINT9 *(REG32_PTR_T)(OTGBASE + 0x628)
141#define HCINTMSK9 *(REG32_PTR_T)(OTGBASE + 0x62C)
142#define HCTSIZ9 *(REG32_PTR_T)(OTGBASE + 0x630)
143#define HCDMA9 *(REG32_PTR_T)(OTGBASE + 0x634)
144#define HCCHAR10 *(REG32_PTR_T)(OTGBASE + 0x640)
145#define HCSPLT10 *(REG32_PTR_T)(OTGBASE + 0x644)
146#define HCINT10 *(REG32_PTR_T)(OTGBASE + 0x648)
147#define HCINTMSK10 *(REG32_PTR_T)(OTGBASE + 0x64C)
148#define HCTSIZ10 *(REG32_PTR_T)(OTGBASE + 0x650)
149#define HCDMA10 *(REG32_PTR_T)(OTGBASE + 0x654)
150#define HCCHAR11 *(REG32_PTR_T)(OTGBASE + 0x660)
151#define HCSPLT11 *(REG32_PTR_T)(OTGBASE + 0x664)
152#define HCINT11 *(REG32_PTR_T)(OTGBASE + 0x668)
153#define HCINTMSK11 *(REG32_PTR_T)(OTGBASE + 0x66C)
154#define HCTSIZ11 *(REG32_PTR_T)(OTGBASE + 0x670)
155#define HCDMA11 *(REG32_PTR_T)(OTGBASE + 0x674)
156#define HCCHAR12 *(REG32_PTR_T)(OTGBASE + 0x680)
157#define HCSPLT12 *(REG32_PTR_T)(OTGBASE + 0x684)
158#define HCINT12 *(REG32_PTR_T)(OTGBASE + 0x688)
159#define HCINTMSK12 *(REG32_PTR_T)(OTGBASE + 0x68C)
160#define HCTSIZ12 *(REG32_PTR_T)(OTGBASE + 0x690)
161#define HCDMA12 *(REG32_PTR_T)(OTGBASE + 0x694)
162#define HCCHAR13 *(REG32_PTR_T)(OTGBASE + 0x6A0)
163#define HCSPLT13 *(REG32_PTR_T)(OTGBASE + 0x6A4)
164#define HCINT13 *(REG32_PTR_T)(OTGBASE + 0x6A8)
165#define HCINTMSK13 *(REG32_PTR_T)(OTGBASE + 0x6AC)
166#define HCTSIZ13 *(REG32_PTR_T)(OTGBASE + 0x6B0)
167#define HCDMA13 *(REG32_PTR_T)(OTGBASE + 0x6B4)
168#define HCCHAR14 *(REG32_PTR_T)(OTGBASE + 0x6C0)
169#define HCSPLT14 *(REG32_PTR_T)(OTGBASE + 0x6C4)
170#define HCINT14 *(REG32_PTR_T)(OTGBASE + 0x6C8)
171#define HCINTMSK14 *(REG32_PTR_T)(OTGBASE + 0x6CC)
172#define HCTSIZ14 *(REG32_PTR_T)(OTGBASE + 0x6D0)
173#define HCDMA14 *(REG32_PTR_T)(OTGBASE + 0x6D4)
174#define HCCHAR15 *(REG32_PTR_T)(OTGBASE + 0x6E0)
175#define HCSPLT15 *(REG32_PTR_T)(OTGBASE + 0x6E4)
176#define HCINT15 *(REG32_PTR_T)(OTGBASE + 0x6E8)
177#define HCINTMSK15 *(REG32_PTR_T)(OTGBASE + 0x6EC)
178#define HCTSIZ15 *(REG32_PTR_T)(OTGBASE + 0x6F0)
179#define HCDMA15 *(REG32_PTR_T)(OTGBASE + 0x6F4)
180
181/*** DEVICE MODE REGISTERS ***/
182/* Device Global Registers */
183#define DCFG *(REG32_PTR_T)(OTGBASE + 0x800)
184#define DCTL *(REG32_PTR_T)(OTGBASE + 0x804)
185#define DSTS *(REG32_PTR_T)(OTGBASE + 0x808)
186#define DIEPMSK *(REG32_PTR_T)(OTGBASE + 0x810)
187#define DOEPMSK *(REG32_PTR_T)(OTGBASE + 0x814)
188#define DAINT *(REG32_PTR_T)(OTGBASE + 0x818)
189#define DAINTMSK *(REG32_PTR_T)(OTGBASE + 0x81C)
190#define DTKNQR1 *(REG32_PTR_T)(OTGBASE + 0x820)
191#define DTKNQR2 *(REG32_PTR_T)(OTGBASE + 0x824)
192#define DVBUSDIS *(REG32_PTR_T)(OTGBASE + 0x828)
193#define DVBUSPULSE *(REG32_PTR_T)(OTGBASE + 0x82C)
194#define DTKNQR3 *(REG32_PTR_T)(OTGBASE + 0x830)
195#define DTKNQR4 *(REG32_PTR_T)(OTGBASE + 0x834)
196
197/* Device Logical IN Endpoint-Specific Registers */
198#define DIEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0x900 + 0x20 * x)
199#define DIEPINT(x) *(REG32_PTR_T)(OTGBASE + 0x908 + 0x20 * x)
200#define DIEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0x910 + 0x20 * x)
201#define DIEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0x914 + 0x20 * x)
202#define DIEPCTL0 *(REG32_PTR_T)(OTGBASE + 0x900)
203#define DIEPINT0 *(REG32_PTR_T)(OTGBASE + 0x908)
204#define DIEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0x910)
205#define DIEPDMA0 *(REG32_PTR_T)(OTGBASE + 0x914)
206#define DIEPCTL1 *(REG32_PTR_T)(OTGBASE + 0x920)
207#define DIEPINT1 *(REG32_PTR_T)(OTGBASE + 0x928)
208#define DIEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0x930)
209#define DIEPDMA1 *(REG32_PTR_T)(OTGBASE + 0x934)
210#define DIEPCTL2 *(REG32_PTR_T)(OTGBASE + 0x940)
211#define DIEPINT2 *(REG32_PTR_T)(OTGBASE + 0x948)
212#define DIEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0x950)
213#define DIEPDMA2 *(REG32_PTR_T)(OTGBASE + 0x954)
214#define DIEPCTL3 *(REG32_PTR_T)(OTGBASE + 0x960)
215#define DIEPINT3 *(REG32_PTR_T)(OTGBASE + 0x968)
216#define DIEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0x970)
217#define DIEPDMA3 *(REG32_PTR_T)(OTGBASE + 0x974)
218#define DIEPCTL4 *(REG32_PTR_T)(OTGBASE + 0x980)
219#define DIEPINT4 *(REG32_PTR_T)(OTGBASE + 0x988)
220#define DIEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0x990)
221#define DIEPDMA4 *(REG32_PTR_T)(OTGBASE + 0x994)
222#define DIEPCTL5 *(REG32_PTR_T)(OTGBASE + 0x9A0)
223#define DIEPINT5 *(REG32_PTR_T)(OTGBASE + 0x9A8)
224#define DIEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0x9B0)
225#define DIEPDMA5 *(REG32_PTR_T)(OTGBASE + 0x9B4)
226#define DIEPCTL6 *(REG32_PTR_T)(OTGBASE + 0x9C0)
227#define DIEPINT6 *(REG32_PTR_T)(OTGBASE + 0x9C8)
228#define DIEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0x9D0)
229#define DIEPDMA6 *(REG32_PTR_T)(OTGBASE + 0x9D4)
230#define DIEPCTL7 *(REG32_PTR_T)(OTGBASE + 0x9E0)
231#define DIEPINT7 *(REG32_PTR_T)(OTGBASE + 0x9E8)
232#define DIEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0x9F0)
233#define DIEPDMA7 *(REG32_PTR_T)(OTGBASE + 0x9F4)
234#define DIEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xA00)
235#define DIEPINT8 *(REG32_PTR_T)(OTGBASE + 0xA08)
236#define DIEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xA10)
237#define DIEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xA14)
238#define DIEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xA20)
239#define DIEPINT9 *(REG32_PTR_T)(OTGBASE + 0xA28)
240#define DIEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xA30)
241#define DIEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xA34)
242#define DIEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xA40)
243#define DIEPINT10 *(REG32_PTR_T)(OTGBASE + 0xA48)
244#define DIEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xA50)
245#define DIEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xA54)
246#define DIEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xA60)
247#define DIEPINT11 *(REG32_PTR_T)(OTGBASE + 0xA68)
248#define DIEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xA70)
249#define DIEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xA74)
250#define DIEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xA80)
251#define DIEPINT12 *(REG32_PTR_T)(OTGBASE + 0xA88)
252#define DIEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xA90)
253#define DIEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xA94)
254#define DIEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xAA0)
255#define DIEPINT13 *(REG32_PTR_T)(OTGBASE + 0xAA8)
256#define DIEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xAB0)
257#define DIEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xAB4)
258#define DIEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xAC0)
259#define DIEPINT14 *(REG32_PTR_T)(OTGBASE + 0xAC8)
260#define DIEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xAD0)
261#define DIEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xAD4)
262#define DIEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xAE0)
263#define DIEPINT15 *(REG32_PTR_T)(OTGBASE + 0xAE8)
264#define DIEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xAF0)
265#define DIEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xAF4)
266
267/* Device Logical OUT Endpoint-Specific Registers */
268#define DOEPCTL(x) *(REG32_PTR_T)(OTGBASE + 0xB00 + 0x20 * x)
269#define DOEPINT(x) *(REG32_PTR_T)(OTGBASE + 0xB08 + 0x20 * x)
270#define DOEPTSIZ(x) *(REG32_PTR_T)(OTGBASE + 0xB10 + 0x20 * x)
271#define DOEPDMA(x) *(REG32_PTR_T)(OTGBASE + 0xB14 + 0x20 * x)
272#define DOEPCTL0 *(REG32_PTR_T)(OTGBASE + 0xB00)
273#define DOEPINT0 *(REG32_PTR_T)(OTGBASE + 0xB08)
274#define DOEPTSIZ0 *(REG32_PTR_T)(OTGBASE + 0xB10)
275#define DOEPDMA0 *(REG32_PTR_T)(OTGBASE + 0xB14)
276#define DOEPCTL1 *(REG32_PTR_T)(OTGBASE + 0xB20)
277#define DOEPINT1 *(REG32_PTR_T)(OTGBASE + 0xB28)
278#define DOEPTSIZ1 *(REG32_PTR_T)(OTGBASE + 0xB30)
279#define DOEPDMA1 *(REG32_PTR_T)(OTGBASE + 0xB34)
280#define DOEPCTL2 *(REG32_PTR_T)(OTGBASE + 0xB40)
281#define DOEPINT2 *(REG32_PTR_T)(OTGBASE + 0xB48)
282#define DOEPTSIZ2 *(REG32_PTR_T)(OTGBASE + 0xB50)
283#define DOEPDMA2 *(REG32_PTR_T)(OTGBASE + 0xB54)
284#define DOEPCTL3 *(REG32_PTR_T)(OTGBASE + 0xB60)
285#define DOEPINT3 *(REG32_PTR_T)(OTGBASE + 0xB68)
286#define DOEPTSIZ3 *(REG32_PTR_T)(OTGBASE + 0xB70)
287#define DOEPDMA3 *(REG32_PTR_T)(OTGBASE + 0xB74)
288#define DOEPCTL4 *(REG32_PTR_T)(OTGBASE + 0xB80)
289#define DOEPINT4 *(REG32_PTR_T)(OTGBASE + 0xB88)
290#define DOEPTSIZ4 *(REG32_PTR_T)(OTGBASE + 0xB90)
291#define DOEPDMA4 *(REG32_PTR_T)(OTGBASE + 0xB94)
292#define DOEPCTL5 *(REG32_PTR_T)(OTGBASE + 0xBA0)
293#define DOEPINT5 *(REG32_PTR_T)(OTGBASE + 0xBA8)
294#define DOEPTSIZ5 *(REG32_PTR_T)(OTGBASE + 0xBB0)
295#define DOEPDMA5 *(REG32_PTR_T)(OTGBASE + 0xBB4)
296#define DOEPCTL6 *(REG32_PTR_T)(OTGBASE + 0xBC0)
297#define DOEPINT6 *(REG32_PTR_T)(OTGBASE + 0xBC8)
298#define DOEPTSIZ6 *(REG32_PTR_T)(OTGBASE + 0xBD0)
299#define DOEPDMA6 *(REG32_PTR_T)(OTGBASE + 0xBD4)
300#define DOEPCTL7 *(REG32_PTR_T)(OTGBASE + 0xBE0)
301#define DOEPINT7 *(REG32_PTR_T)(OTGBASE + 0xBE8)
302#define DOEPTSIZ7 *(REG32_PTR_T)(OTGBASE + 0xBF0)
303#define DOEPDMA7 *(REG32_PTR_T)(OTGBASE + 0xBF4)
304#define DOEPCTL8 *(REG32_PTR_T)(OTGBASE + 0xC00)
305#define DOEPINT8 *(REG32_PTR_T)(OTGBASE + 0xC08)
306#define DOEPTSIZ8 *(REG32_PTR_T)(OTGBASE + 0xC10)
307#define DOEPDMA8 *(REG32_PTR_T)(OTGBASE + 0xC14)
308#define DOEPCTL9 *(REG32_PTR_T)(OTGBASE + 0xC20)
309#define DOEPINT9 *(REG32_PTR_T)(OTGBASE + 0xC28)
310#define DOEPTSIZ9 *(REG32_PTR_T)(OTGBASE + 0xC30)
311#define DOEPDMA9 *(REG32_PTR_T)(OTGBASE + 0xC34)
312#define DOEPCTL10 *(REG32_PTR_T)(OTGBASE + 0xC40)
313#define DOEPINT10 *(REG32_PTR_T)(OTGBASE + 0xC48)
314#define DOEPTSIZ10 *(REG32_PTR_T)(OTGBASE + 0xC50)
315#define DOEPDMA10 *(REG32_PTR_T)(OTGBASE + 0xC54)
316#define DOEPCTL11 *(REG32_PTR_T)(OTGBASE + 0xC60)
317#define DOEPINT11 *(REG32_PTR_T)(OTGBASE + 0xC68)
318#define DOEPTSIZ11 *(REG32_PTR_T)(OTGBASE + 0xC70)
319#define DOEPDMA11 *(REG32_PTR_T)(OTGBASE + 0xC74)
320#define DOEPCTL12 *(REG32_PTR_T)(OTGBASE + 0xC80)
321#define DOEPINT12 *(REG32_PTR_T)(OTGBASE + 0xC88)
322#define DOEPTSIZ12 *(REG32_PTR_T)(OTGBASE + 0xC90)
323#define DOEPDMA12 *(REG32_PTR_T)(OTGBASE + 0xC94)
324#define DOEPCTL13 *(REG32_PTR_T)(OTGBASE + 0xCA0)
325#define DOEPINT13 *(REG32_PTR_T)(OTGBASE + 0xCA8)
326#define DOEPTSIZ13 *(REG32_PTR_T)(OTGBASE + 0xCB0)
327#define DOEPDMA13 *(REG32_PTR_T)(OTGBASE + 0xCB4)
328#define DOEPCTL14 *(REG32_PTR_T)(OTGBASE + 0xCC0)
329#define DOEPINT14 *(REG32_PTR_T)(OTGBASE + 0xCC8)
330#define DOEPTSIZ14 *(REG32_PTR_T)(OTGBASE + 0xCD0)
331#define DOEPDMA14 *(REG32_PTR_T)(OTGBASE + 0xCD4)
332#define DOEPCTL15 *(REG32_PTR_T)(OTGBASE + 0xCE0)
333#define DOEPINT15 *(REG32_PTR_T)(OTGBASE + 0xCE8)
334#define DOEPTSIZ15 *(REG32_PTR_T)(OTGBASE + 0xCF0)
335#define DOEPDMA15 *(REG32_PTR_T)(OTGBASE + 0xCF4)
336
337/* Power and Clock Gating Register */
338#define PCGCCTL *(REG32_PTR_T)(OTGBASE + 0xE00)
339
340
341#endif /* USB_S3C6400X_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-05 00:46:28 +0000