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author | Rafaël Carré <rafael.carre@gmail.com> | 2008-10-28 11:24:29 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2008-10-28 11:24:29 +0000 |
commit | b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3 (patch) | |
tree | 666598d06ac756ba58dedab7c53ea4bd667e0b0d /firmware | |
parent | a5a2f12f0a07df1f58732e1d6cb08a5d730fc79c (diff) | |
download | rockbox-b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3.tar.gz rockbox-b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3.zip |
Sansav2 : initializes SDRAM
The AS3525 SoC ships with an ARM PL172 MPMC controller
Also correct the memory sizes in tools/configure
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18899 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/as3525.h | 35 | ||||
-rw-r--r-- | firmware/target/arm/as3525/system-as3525.c | 76 |
2 files changed, 110 insertions, 1 deletions
diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index 2453c33ec0..91d0155234 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h | |||
@@ -312,4 +312,39 @@ interface */ | |||
312 | #define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420)) | 312 | #define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420)) |
313 | #define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a)))) | 313 | #define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a)))) |
314 | 314 | ||
315 | /* ARM PL172 Memory Controller registers */ | ||
316 | |||
317 | #define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000)) | ||
318 | #define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004)) | ||
319 | #define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008)) | ||
320 | |||
321 | #define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020)) | ||
322 | #define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024)) | ||
323 | #define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028)) | ||
324 | #define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030)) | ||
325 | #define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034)) | ||
326 | #define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038)) | ||
327 | #define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C)) | ||
328 | #define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040)) | ||
329 | #define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044)) | ||
330 | #define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048)) | ||
331 | #define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C)) | ||
332 | #define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050)) | ||
333 | #define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054)) | ||
334 | #define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058)) | ||
335 | |||
336 | #define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080)) | ||
337 | |||
338 | #define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100)) | ||
339 | #define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120)) | ||
340 | #define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140)) | ||
341 | #define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160)) | ||
342 | |||
343 | #define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104)) | ||
344 | #define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124)) | ||
345 | #define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144)) | ||
346 | #define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164)) | ||
347 | |||
348 | #define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8)) | ||
349 | |||
315 | #endif /*__AS3525_H__*/ | 350 | #endif /*__AS3525_H__*/ |
diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 2df8eee7e5..e83e5150ae 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c | |||
@@ -8,6 +8,7 @@ | |||
8 | * $Id$ | 8 | * $Id$ |
9 | * | 9 | * |
10 | * Copyright (C) 2007 by Rob Purchase | 10 | * Copyright (C) 2007 by Rob Purchase |
11 | * Copyright © 2008 Rafaël Carré | ||
11 | * | 12 | * |
12 | * This program is free software; you can redistribute it and/or | 13 | * This program is free software; you can redistribute it and/or |
13 | * modify it under the terms of the GNU General Public License | 14 | * modify it under the terms of the GNU General Public License |
@@ -124,10 +125,83 @@ void fiq_handler(void) | |||
124 | ); | 125 | ); |
125 | } | 126 | } |
126 | 127 | ||
128 | static void sdram_delay(void) | ||
129 | { | ||
130 | int delay = 1024; /* arbitrary */ | ||
131 | while (delay--) ; | ||
132 | } | ||
133 | |||
134 | /* Use the same initialization than OF */ | ||
135 | static void sdram_init(void) | ||
136 | { | ||
137 | CGU_PERI &= ~(0xf<<2); /* clear div0 (memclock) */ | ||
138 | CGU_PERI |= (1<<2); /* divider = 2 */ | ||
139 | |||
140 | CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */ | ||
141 | |||
142 | MPMC_CONTROL = 0x1; /* enable MPMC */ | ||
143 | |||
144 | MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */ | ||
145 | sdram_delay(); | ||
146 | |||
147 | MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */ | ||
148 | sdram_delay(); | ||
149 | |||
150 | MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */ | ||
151 | |||
152 | MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */ | ||
153 | |||
154 | if(MPMC_PERIPH_ID2 & 0xf0) | ||
155 | MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */ | ||
156 | |||
157 | /* timings */ | ||
158 | MPMC_DYNAMIC_tRP = 2; | ||
159 | MPMC_DYNAMIC_tRAS = 4; | ||
160 | MPMC_DYNAMIC_tSREX = 5; | ||
161 | MPMC_DYNAMIC_tAPR = 0; | ||
162 | MPMC_DYNAMIC_tDAL = 4; | ||
163 | MPMC_DYNAMIC_tWR = 2; | ||
164 | MPMC_DYNAMIC_tRC = 5; | ||
165 | MPMC_DYNAMIC_tRFC = 5; | ||
166 | MPMC_DYNAMIC_tXSR = 5; | ||
167 | MPMC_DYNAMIC_tRRD = 2; | ||
168 | MPMC_DYNAMIC_tMRD = 2; | ||
169 | |||
170 | #if defined(SANSA_CLIP) || defined(SANSA_M200V2) | ||
171 | # define MEMORY_MODEL 0x21 | ||
172 | /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */ | ||
173 | #elif defined(SANSA_E200V2) | ||
174 | # define MEMORY_MODEL 0x5 | ||
175 | /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */ | ||
176 | #else | ||
177 | # error "The external memory in your player is unknown" | ||
178 | #endif | ||
179 | |||
180 | MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */ | ||
181 | MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7); | ||
182 | |||
183 | MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 = | ||
184 | MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 = | ||
185 | MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0; | ||
186 | |||
187 | MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */ | ||
188 | |||
189 | /* this part is required, if you know why please explain */ | ||
190 | unsigned int tmp = *(volatile unsigned int*)(0x30000000+0x2300*MEM); | ||
191 | (void)tmp; /* we just need to read from this location */ | ||
192 | |||
193 | MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */ | ||
194 | |||
195 | MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */ | ||
196 | } | ||
127 | 197 | ||
128 | void system_init(void) | 198 | void system_init(void) |
129 | { | 199 | { |
130 | /* CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; */ | 200 | #if 0 /* the GPIO clock is already enabled by the dualboot function */ |
201 | CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; | ||
202 | #endif | ||
203 | |||
204 | sdram_init(); | ||
131 | } | 205 | } |
132 | 206 | ||
133 | void system_reboot(void) | 207 | void system_reboot(void) |