From b3ee07c22e1886c4cb1557dbaa4fd65d25cd1be3 Mon Sep 17 00:00:00 2001 From: Rafaël Carré Date: Tue, 28 Oct 2008 11:24:29 +0000 Subject: Sansav2 : initializes SDRAM The AS3525 SoC ships with an ARM PL172 MPMC controller Also correct the memory sizes in tools/configure git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18899 a1c6a512-1295-4272-9138-f99709370657 --- firmware/export/as3525.h | 35 ++++++++++++++ firmware/target/arm/as3525/system-as3525.c | 76 +++++++++++++++++++++++++++++- 2 files changed, 110 insertions(+), 1 deletion(-) (limited to 'firmware') diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index 2453c33ec0..91d0155234 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h @@ -312,4 +312,39 @@ interface */ #define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420)) #define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+4*(1<<(a)))) +/* ARM PL172 Memory Controller registers */ + +#define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000)) +#define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004)) +#define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008)) + +#define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020)) +#define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024)) +#define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028)) +#define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030)) +#define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034)) +#define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038)) +#define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C)) +#define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040)) +#define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044)) +#define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048)) +#define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C)) +#define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050)) +#define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054)) +#define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058)) + +#define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080)) + +#define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100)) +#define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120)) +#define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140)) +#define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160)) + +#define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104)) +#define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124)) +#define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144)) +#define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164)) + +#define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8)) + #endif /*__AS3525_H__*/ diff --git a/firmware/target/arm/as3525/system-as3525.c b/firmware/target/arm/as3525/system-as3525.c index 2df8eee7e5..e83e5150ae 100644 --- a/firmware/target/arm/as3525/system-as3525.c +++ b/firmware/target/arm/as3525/system-as3525.c @@ -8,6 +8,7 @@ * $Id$ * * Copyright (C) 2007 by Rob Purchase + * Copyright © 2008 Rafaël Carré * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -124,10 +125,83 @@ void fiq_handler(void) ); } +static void sdram_delay(void) +{ + int delay = 1024; /* arbitrary */ + while (delay--) ; +} + +/* Use the same initialization than OF */ +static void sdram_init(void) +{ + CGU_PERI &= ~(0xf<<2); /* clear div0 (memclock) */ + CGU_PERI |= (1<<2); /* divider = 2 */ + + CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */ + + MPMC_CONTROL = 0x1; /* enable MPMC */ + + MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */ + sdram_delay(); + + MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */ + sdram_delay(); + + MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */ + + MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */ + + if(MPMC_PERIPH_ID2 & 0xf0) + MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */ + + /* timings */ + MPMC_DYNAMIC_tRP = 2; + MPMC_DYNAMIC_tRAS = 4; + MPMC_DYNAMIC_tSREX = 5; + MPMC_DYNAMIC_tAPR = 0; + MPMC_DYNAMIC_tDAL = 4; + MPMC_DYNAMIC_tWR = 2; + MPMC_DYNAMIC_tRC = 5; + MPMC_DYNAMIC_tRFC = 5; + MPMC_DYNAMIC_tXSR = 5; + MPMC_DYNAMIC_tRRD = 2; + MPMC_DYNAMIC_tMRD = 2; + +#if defined(SANSA_CLIP) || defined(SANSA_M200V2) +# define MEMORY_MODEL 0x21 + /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */ +#elif defined(SANSA_E200V2) +# define MEMORY_MODEL 0x5 + /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */ +#else +# error "The external memory in your player is unknown" +#endif + + MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */ + MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7); + + MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 = + MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 = + MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0; + + MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */ + + /* this part is required, if you know why please explain */ + unsigned int tmp = *(volatile unsigned int*)(0x30000000+0x2300*MEM); + (void)tmp; /* we just need to read from this location */ + + MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */ + + MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */ +} void system_init(void) { -/* CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; */ +#if 0 /* the GPIO clock is already enabled by the dualboot function */ + CGU_PERI |= CGU_GPIO_CLOCK_ENABLE; +#endif + + sdram_init(); } void system_reboot(void) -- cgit v1.2.3