diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 13:46:04 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2010-04-23 13:46:04 +0000 |
commit | 6cee7579dbdc4d41c4df08c9395cf96c952ebab1 (patch) | |
tree | cd62801c3dc65be5923aa156ef9d5c2726629664 /firmware | |
parent | 57dc493db55ec9388e3e3a3eb848fffccb07b301 (diff) | |
download | rockbox-6cee7579dbdc4d41c4df08c9395cf96c952ebab1.tar.gz rockbox-6cee7579dbdc4d41c4df08c9395cf96c952ebab1.zip |
i.MX31: Add some enums and a couple helper functions to make dealing with pin muxing and pad configuration a bit more sane. Convert any existing code which changes mux/pad settings to use helpers.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25698 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/SOURCES | 1 | ||||
-rw-r--r-- | firmware/export/imx31l.h | 305 | ||||
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | 43 | ||||
-rw-r--r-- | firmware/target/arm/imx31/iomuxc-imx31.c | 50 | ||||
-rw-r--r-- | firmware/target/arm/imx31/iomuxc-imx31.h | 364 |
5 files changed, 482 insertions, 281 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index ac3adacab4..b69d51af62 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -877,6 +877,7 @@ target/arm/imx31/debug-imx31.c | |||
877 | target/arm/imx31/dvfs_dptc-imx31.c | 877 | target/arm/imx31/dvfs_dptc-imx31.c |
878 | target/arm/imx31/gpio-imx31.c | 878 | target/arm/imx31/gpio-imx31.c |
879 | target/arm/imx31/i2c-imx31.c | 879 | target/arm/imx31/i2c-imx31.c |
880 | target/arm/imx31/iomuxc-imx31.c | ||
880 | target/arm/imx31/mc13783-imx31.c | 881 | target/arm/imx31/mc13783-imx31.c |
881 | target/arm/imx31/mmu-imx31.c | 882 | target/arm/imx31/mmu-imx31.c |
882 | target/arm/imx31/rolo_restart.S | 883 | target/arm/imx31/rolo_restart.S |
diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index 6ad50f0a16..3f94156650 100644 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h | |||
@@ -135,269 +135,56 @@ | |||
135 | #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */ | 135 | #define IIM_SREV_2_0_1L 0x29 /* i.MX31L 2.0/2.0.1, M91E */ |
136 | 136 | ||
137 | /* IOMUXC */ | 137 | /* IOMUXC */ |
138 | #define IOMUXC_(o) (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+(o))) | 138 | #define IOMUXC_GPR (*(REG32_PTR_T)(IOMUXC_BASE_ADDR+0x008)) |
139 | 139 | ||
140 | /* GPR */ | 140 | /* SW_MUX_CTL_* */ |
141 | #define IOMUXC_GPR IOMUXC_(0x008) | 141 | #define IOMUXC_MUX_OUT (0x7 << 4) |
142 | 142 | #define IOMUXC_MUX_OUT_POS (4) | |
143 | /* SW_MUX_CTL */ | 143 | #define IOMUXC_MUX_IN (0xf << 0) |
144 | #define SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD IOMUXC_(0x00C) | 144 | #define IOMUXC_MUX_IN_POS (0) |
145 | #define SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x010) | 145 | #define IOMUXC_MUX_MASK (0x7f) |
146 | #define SW_MUX_CTL_ATA_CS1_ATA_DIOR_ATA_DIOW_ATA_DMACK IOMUXC_(0x014) | 146 | |
147 | #define SW_MUX_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3_ATA_CS0 IOMUXC_(0x018) | 147 | #define IOMUXC_MUX_OUT_GPIO (0x0 << IOMUXC_MUX_OUT_POS) |
148 | #define SW_MUX_CTL_D3_SPL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x01C) | 148 | #define IOMUXC_MUX_OUT_FUNCTIONAL (0x1 << IOMUXC_MUX_OUT_POS) |
149 | #define SW_MUX_CTL_VSYNC3_CONTRAST_D3_REV_D3_CLS IOMUXC_(0x020) | 149 | #define IOMUXC_MUX_OUT_ALT1 (0x2 << IOMUXC_MUX_OUT_POS) |
150 | #define SW_MUX_CTL_SER_RS_PAR_RS_WRITE_READ IOMUXC_(0x024) | 150 | #define IOMUXC_MUX_OUT_ALT2 (0x3 << IOMUXC_MUX_OUT_POS) |
151 | #define SW_MUX_CTL_SD_D_IO_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x028) | 151 | #define IOMUXC_MUX_OUT_ALT3 (0x4 << IOMUXC_MUX_OUT_POS) |
152 | #define SW_MUX_CTL_HSYNC_FPSHIFT_DRDY0_SD_D_I IOMUXC_(0x02C) | 152 | #define IOMUXC_MUX_OUT_ALT4 (0x5 << IOMUXC_MUX_OUT_POS) |
153 | #define SW_MUX_CTL_LD15_LD16_LD17_VSYNC0 IOMUXC_(0x030) | 153 | #define IOMUXC_MUX_OUT_ALT5 (0x6 << IOMUXC_MUX_OUT_POS) |
154 | #define SW_MUX_CTL_LD11_LD12_LD13_LD14 IOMUXC_(0x034) | 154 | #define IOMUXC_MUX_OUT_ALT6 (0x7 << IOMUXC_MUX_OUT_POS) |
155 | #define SW_MUX_CTL_LD7_LD8_LD9_LD10 IOMUXC_(0x038) | 155 | |
156 | #define SW_MUX_CTL_LD3_LD4_LD5_LD6 IOMUXC_(0x03C) | 156 | #define IOMUXC_MUX_IN_NONE (0x0 << IOMUXC_MUX_IN_POS) |
157 | #define SW_MUX_CTL_USBH2_DATA1_LD0_LD1_LD2 IOMUXC_(0x040) | 157 | #define IOMUXC_MUX_IN_GPIO (0x1 << IOMUXC_MUX_IN_POS) |
158 | #define SW_MUX_CTL_USBH2_DIR_USBH2_STP_USBH2_NXT_USBH2_DATA0 IOMUXC_(0x044) | 158 | #define IOMUXC_MUX_IN_FUNCTIONAL (0x2 << IOMUXC_MUX_IN_POS) |
159 | #define SW_MUX_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7_USBH2_CLK IOMUXC_(0x048) | 159 | #define IOMUXC_MUX_IN_ALT1 (0x4 << IOMUXC_MUX_IN_POS) |
160 | #define SW_MUX_CTL_USBOTG_DATA1_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x04C) | 160 | #define IOMUXC_MUX_IN_ALT2 (0x8 << IOMUXC_MUX_IN_POS) |
161 | #define SW_MUX_CTL_USBOTG_DIR_USBOTG_STP_USBOTG_NXT_USBOTG_DATA0 IOMUXC_(0x050) | 161 | |
162 | #define SW_MUX_CTL_USB_PWR_USB_OC_USB_BYP_USBOTG_CLK IOMUXC_(0x054) | 162 | /* SW_PAD_CTL_* */ |
163 | #define SW_MUX_CTL_TDO_TRSTB_DE_B_SJC_MOD IOMUXC_(0x058) | 163 | #define IOMUXC_PAD_LOOPBACK (0x1 << 9) /* Route output to input */ |
164 | #define SW_MUX_CTL_RTCK_TCK_TMS_TDI IOMUXC_(0x05C) | ||
165 | #define SW_MUX_CTL_KEY_COL4_KEY_COL5_KEY_COL6_KEY_COL7 IOMUXC_(0x060) | ||
166 | #define SW_MUX_CTL_KEY_COL0_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x064) | ||
167 | #define SW_MUX_CTL_KEY_ROW4_KEY_ROW5_KEY_ROW6_KEY_ROW7 IOMUXC_(0x068) | ||
168 | #define SW_MUX_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2_KEY_ROW3 IOMUXC_(0x06C) | ||
169 | #define SW_MUX_CTL_TXD2_RTS2_CTS2_BATT_LINE IOMUXC_(0x070) | ||
170 | #define SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2 IOMUXC_(0x074) | ||
171 | #define SW_MUX_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1_DSR_DTE1 IOMUXC_(0x078) | ||
172 | #define SW_MUX_CTL_RTS1_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x07C) | ||
173 | #define SW_MUX_CTL_CSPI2_SCLK_CSPI2_SPI_RDY_RXD1_TXD1 IOMUXC_(0x080) | ||
174 | #define SW_MUX_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1_CSPI2_SS2 IOMUXC_(0x084) | ||
175 | #define SW_MUX_CTL_CSPI1_SS2_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x088) | ||
176 | #define SW_MUX_CTL_CSPI1_MOSI_CSPI1_MISO_CSPI1_SS0_CSPI1_SS1 IOMUXC_(0x08C) | ||
177 | #define SW_MUX_CTL_STXD6_SRXD6_SCK6_SFS6 IOMUXC_(0x090) | ||
178 | #define SW_MUX_CTL_STXD5_SRXD5_SCK5_SFS5 IOMUXC_(0x094) | ||
179 | #define SW_MUX_CTL_STXD4_SRXD4_SCK4_SFS4 IOMUXC_(0x098) | ||
180 | #define SW_MUX_CTL_STXD3_SRXD3_SCK3_SFS3 IOMUXC_(0x09C) | ||
181 | #define SW_MUX_CTL_CSI_HSYNC_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x0A0) | ||
182 | #define SW_MUX_CTL_CSI_D14_CSI_D15_CSI_MCLK_CSI_VSYNC IOMUXC_(0x0A4) | ||
183 | #define SW_MUX_CTL_CSI_D10_CSI_D11_CSI_D12_CSI_D13 IOMUXC_(0x0A8) | ||
184 | #define SW_MUX_CTL_CSI_D6_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x0AC) | ||
185 | #define SW_MUX_CTL_M_REQUEST_M_GRANT_CSI_D4_CSI_D5 IOMUXC_(0x0B0) | ||
186 | #define SW_MUX_CTL_PC_RST_IOIS16_PC_RW_B_PC_POE IOMUXC_(0x0B4) | ||
187 | #define SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x0B8) | ||
188 | #define SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON IOMUXC_(0x0BC) | ||
189 | #define SW_MUX_CTL_D2_D1_D0_PC_CD1_B IOMUXC_(0x0C0) | ||
190 | #define SW_MUX_CTL_D6_D5_D4_D3 IOMUXC_(0x0C4) | ||
191 | #define SW_MUX_CTL_D10_D9_D8_D7 IOMUXC_(0x0C8) | ||
192 | #define SW_MUX_CTL_D14_D13_D12_D11 IOMUXC_(0x0CC) | ||
193 | #define SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15 IOMUXC_(0x0D0) | ||
194 | #define SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE IOMUXC_(0x0D4) | ||
195 | #define SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3 IOMUXC_(0x0D8) | ||
196 | #define SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x0DC) | ||
197 | #define SW_MUX_CTL_RW_RAS_CAS_SDWE IOMUXC_(0x0E0) | ||
198 | #define SW_MUX_CTL_CS5_ECB_LBA_BCLK IOMUXC_(0x0E4) | ||
199 | #define SW_MUX_CTL_CS1_CS2_CS3_CS4 IOMUXC_(0x0E8) | ||
200 | #define SW_MUX_CTL_EB0_EB1_OE_CS0 IOMUXC_(0x0EC) | ||
201 | #define SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3 IOMUXC_(0x0F0) | ||
202 | #define SW_MUX_CTL_SD28_SD29_SD30_SD31 IOMUXC_(0x0F4) | ||
203 | #define SW_MUX_CTL_SD24_SD25_SD26_SD27 IOMUXC_(0x0F8) | ||
204 | #define SW_MUX_CTL_SD20_SD21_SD22_SD23 IOMUXC_(0x0FC) | ||
205 | #define SW_MUX_CTL_SD16_SD17_SD18_SD19 IOMUXC_(0x100) | ||
206 | #define SW_MUX_CTL_SD12_SD13_SD14_SD15 IOMUXC_(0x104) | ||
207 | #define SW_MUX_CTL_SD8_SD9_SD10_SD11 IOMUXC_(0x108) | ||
208 | #define SW_MUX_CTL_SD4_SD5_SD6_SD7 IOMUXC_(0x10C) | ||
209 | #define SW_MUX_CTL_SD0_SD1_SD2_SD3 IOMUXC_(0x110) | ||
210 | #define SW_MUX_CTL_A24_A25_SDBA1_SDBA0 IOMUXC_(0x114) | ||
211 | #define SW_MUX_CTL_A20_A21_A22_A23 IOMUXC_(0x118) | ||
212 | #define SW_MUX_CTL_A16_A17_A18_A19 IOMUXC_(0x11C) | ||
213 | #define SW_MUX_CTL_A12_A13_A14_A15 IOMUXC_(0x120) | ||
214 | #define SW_MUX_CTL_A9_A10_MA10_A11 IOMUXC_(0x124) | ||
215 | #define SW_MUX_CTL_A5_A6_A7_A8 IOMUXC_(0x128) | ||
216 | #define SW_MUX_CTL_A1_A2_A3_A4 IOMUXC_(0x12C) | ||
217 | #define SW_MUX_CTL_DVFS1_VPG0_VPG1_A0 IOMUXC_(0x130) | ||
218 | #define SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0 IOMUXC_(0x134) | ||
219 | #define SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4 IOMUXC_(0x138) | ||
220 | #define SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x13C) | ||
221 | #define SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH IOMUXC_(0x140) | ||
222 | #define SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0 IOMUXC_(0x144) | ||
223 | #define SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x148) | ||
224 | #define SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3 IOMUXC_(0x14C) | ||
225 | #define SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO IOMUXC_(0x150) | ||
226 | |||
227 | #define SW_MUX_OUT (0x7 << 4) | ||
228 | #define SW_MUX_OUT_GPIO_DR (0x0 << 4) | ||
229 | #define SW_MUX_OUT_FUNCTIONAL (0x1 << 4) | ||
230 | #define SW_MUX_OUT_ALT1 (0x2 << 4) | ||
231 | #define SW_MUX_OUT_ALT2 (0x3 << 4) | ||
232 | #define SW_MUX_OUT_ALT3 (0x4 << 4) | ||
233 | #define SW_MUX_OUT_ALT4 (0x5 << 4) | ||
234 | #define SW_MUX_OUT_ALT5 (0x6 << 4) | ||
235 | #define SW_MUX_OUT_ALT6 (0x7 << 4) | ||
236 | |||
237 | #define SW_MUX_IN (0xf << 0) | ||
238 | #define SW_MUX_IN_NO_INPUTS (0x0 << 0) | ||
239 | #define SW_MUX_IN_GPIO_PSR_ISR (0x1 << 0) | ||
240 | #define SW_MUX_IN_FUNCTIONAL (0x2 << 0) | ||
241 | #define SW_MUX_IN_ALT1 (0x4 << 0) | ||
242 | #define SW_MUX_IN_ALT2 (0x8 << 0) | ||
243 | |||
244 | /* Masks for each signal field */ | ||
245 | #define SW_MUX_CTL_SIG1 (0x7f << 0) | ||
246 | #define SW_MUX_CTL_SIG2 (0x7f << 8) | ||
247 | #define SW_MUX_CTL_SIG3 (0x7f << 16) | ||
248 | #define SW_MUX_CTL_SIG4 (0x7f << 24) | ||
249 | /* Shift above flags into one of the four fields in each register */ | ||
250 | #define SW_MUX_CTL_SIG1_POS (0) | ||
251 | #define SW_MUX_CTL_SIG2_POS (8) | ||
252 | #define SW_MUX_CTL_SIG3_POS (16) | ||
253 | #define SW_MUX_CTL_SIG4_POS (24) | ||
254 | |||
255 | /* SW_PAD_CTL */ | ||
256 | #define SW_PAD_CTL_TTM_PAD__X__X IOMUXC_(0x154) | ||
257 | #define SW_PAD_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY IOMUXC_(0x158) | ||
258 | #define SW_PAD_CTL_CE_CONTROL_CLKSS_CSPI3_MOSI IOMUXC_(0x15C) | ||
259 | #define SW_PAD_CTL_ATA_DIOW_ATA_DMACK_ATA_RESET_B IOMUXC_(0x160) | ||
260 | #define SW_PAD_CTL_ATA_CS0_ATA_CS1_ATA_DIOR IOMUXC_(0x164) | ||
261 | #define SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3 IOMUXC_(0x168) | ||
262 | #define SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0 IOMUXC_(0x16C) | ||
263 | #define SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL IOMUXC_(0x170) | ||
264 | #define SW_PAD_CTL_READ_VSYNC3_CONTRAST IOMUXC_(0x174) | ||
265 | #define SW_PAD_CTL_SER_RS_PAR_RS_WRITE IOMUXC_(0x178) | ||
266 | #define SW_PAD_CTL_SD_D_CLK_LCS0_LCS1 IOMUXC_(0x17C) | ||
267 | #define SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO IOMUXC_(0x180) | ||
268 | #define SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT IOMUXC_(0x184) | ||
269 | #define SW_PAD_CTL_LD15_LD16_LD17 IOMUXC_(0x188) | ||
270 | #define SW_PAD_CTL_LD12_LD13_LD14 IOMUXC_(0x18C) | ||
271 | #define SW_PAD_CTL_LD9_LD10_LD11 IOMUXC_(0x190) | ||
272 | #define SW_PAD_CTL_LD6_LD7_LD8 IOMUXC_(0x194) | ||
273 | #define SW_PAD_CTL_LD3_LD4_LD5 IOMUXC_(0x198) | ||
274 | #define SW_PAD_CTL_LD0_LD1_LD2 IOMUXC_(0x19C) | ||
275 | #define SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1 IOMUXC_(0x1A0) | ||
276 | #define SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP IOMUXC_(0x1A4) | ||
277 | #define SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7 IOMUXC_(0x1A8) | ||
278 | #define SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4 IOMUXC_(0x1AC) | ||
279 | #define SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1 IOMUXC_(0x1B0) | ||
280 | #define SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP IOMUXC_(0x1B4) | ||
281 | #define SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP IOMUXC_(0x1B8) | ||
282 | #define SW_PAD_CTL_TRSTB_DE_B_SJC_MOD IOMUXC_(0x1BC) | ||
283 | #define SW_PAD_CTL_TMS_TDI_TDO IOMUXC_(0x1C0) | ||
284 | #define SW_PAD_CTL_KEY_COL7_RTCK_TCK IOMUXC_(0x1C4) | ||
285 | #define SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6 IOMUXC_(0x1C8) | ||
286 | #define SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3 IOMUXC_(0x1CC) | ||
287 | #define SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0 IOMUXC_(0x1D0) | ||
288 | #define SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5 IOMUXC_(0x1D4) | ||
289 | #define SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2 IOMUXC_(0x1D8) | ||
290 | #define SW_PAD_CTL_RTS2_CTS2_BATT_LINE IOMUXC_(0x1DC) | ||
291 | #define SW_PAD_CTL_DTR_DCE2_RXD2_TXD2 IOMUXC_(0x1E0) | ||
292 | #define SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1 IOMUXC_(0x1E4) | ||
293 | #define SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1 IOMUXC_(0x1E8) | ||
294 | #define SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1 IOMUXC_(0x1EC) | ||
295 | #define SW_PAD_CTL_RXD1_TXD1_RTS1 IOMUXC_(0x1F0) | ||
296 | #define SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY IOMUXC_(0x1F4) | ||
297 | #define SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1 IOMUXC_(0x1F8) | ||
298 | #define SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI IOMUXC_(0x1FC) | ||
299 | #define SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS IOMUXC_(0x200) | ||
300 | #define SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO IOMUXC_(0x204) | ||
301 | #define SW_PAD_CTL_STXD6_SRXD6_SCK6 IOMUXC_(0x208) | ||
302 | #define SW_PAD_CTL_SRXD5_SCK5_SFS5 IOMUXC_(0x20C) | ||
303 | #define SW_PAD_CTL_SCK4_SFS4_STXD5 IOMUXC_(0x210) | ||
304 | #define SW_PAD_CTL_SFS3_STXD4_SRXD4 IOMUXC_(0x214) | ||
305 | #define SW_PAD_CTL_STXD3_SRXD3_SCK3 IOMUXC_(0x218) | ||
306 | #define SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT IOMUXC_(0x21C) | ||
307 | #define SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC IOMUXC_(0x220) | ||
308 | #define SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15 IOMUXC_(0x224) | ||
309 | #define SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12 IOMUXC_(0x228) | ||
310 | #define SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9 IOMUXC_(0x22C) | ||
311 | #define SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6 IOMUXC_(0x230) | ||
312 | #define SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT IOMUXC_(0x234) | ||
313 | #define SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B IOMUXC_(0x238) | ||
314 | #define SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2 IOMUXC_(0x23C) | ||
315 | #define SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1 IOMUXC_(0x240) | ||
316 | #define SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B IOMUXC_(0x244) | ||
317 | #define SW_PAD_CTL_D2_D1_D0 IOMUXC_(0x248) | ||
318 | #define SW_PAD_CTL_D5_D4_D3 IOMUXC_(0x24C) | ||
319 | #define SW_PAD_CTL_D8_D7_D6 IOMUXC_(0x250) | ||
320 | #define SW_PAD_CTL_D11_D10_D9 IOMUXC_(0x254) | ||
321 | #define SW_PAD_CTL_D14_D13_D12 IOMUXC_(0x258) | ||
322 | #define SW_PAD_CTL_NFCE_B_NFRB_D15 IOMUXC_(0x25C) | ||
323 | #define SW_PAD_CTL_NFALE_NFCLE_NFWP_B IOMUXC_(0x260) | ||
324 | #define SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B IOMUXC_(0x264) | ||
325 | #define SW_PAD_CTL_SDQS0_SDQS1_SDQS2 IOMUXC_(0x268) | ||
326 | #define SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B IOMUXC_(0x26C) | ||
327 | #define SW_PAD_CTL_CAS_SDWE_SDCKE0 IOMUXC_(0x270) | ||
328 | #define SW_PAD_CTL_BCLK_RW_RAS IOMUXC_(0x274) | ||
329 | #define SW_PAD_CTL_CS5_ECB_LBA IOMUXC_(0x278) | ||
330 | #define SW_PAD_CTL_CS2_CS3_CS4 IOMUXC_(0x27C) | ||
331 | #define SW_PAD_CTL_OE_CS0_CS1 IOMUXC_(0x280) | ||
332 | #define SW_PAD_CTL_DQM3_EB0_EB1 IOMUXC_(0x284) | ||
333 | #define SW_PAD_CTL_DQM0_DQM1_DQM2 IOMUXC_(0x288) | ||
334 | #define SW_PAD_CTL_SD29_SD30_SD31 IOMUXC_(0x28C) | ||
335 | #define SW_PAD_CTL_SD26_SD27_SD28 IOMUXC_(0x290) | ||
336 | #define SW_PAD_CTL_SD23_SD24_SD25 IOMUXC_(0x294) | ||
337 | #define SW_PAD_CTL_SD20_SD21_SD22 IOMUXC_(0x298) | ||
338 | #define SW_PAD_CTL_SD17_SD18_SD19 IOMUXC_(0x29C) | ||
339 | #define SW_PAD_CTL_SD14_SD15_SD16 IOMUXC_(0x2A0) | ||
340 | #define SW_PAD_CTL_SD11_SD12_SD13 IOMUXC_(0x2A4) | ||
341 | #define SW_PAD_CTL_SD8_SD9_SD10 IOMUXC_(0x2A8) | ||
342 | #define SW_PAD_CTL_SD5_SD6_SD7 IOMUXC_(0x2AC) | ||
343 | #define SW_PAD_CTL_SD2_SD3_SD4 IOMUXC_(0x2B0) | ||
344 | #define SW_PAD_CTL_SDBA0_SD0_SD1 IOMUXC_(0x2B4) | ||
345 | #define SW_PAD_CTL_A24_A25_SDBA1 IOMUXC_(0x2B8) | ||
346 | #define SW_PAD_CTL_A21_A22_A23 IOMUXC_(0x2BC) | ||
347 | #define SW_PAD_CTL_A18_A19_A20 IOMUXC_(0x2C0) | ||
348 | #define SW_PAD_CTL_A15_A16_A17 IOMUXC_(0x2C4) | ||
349 | #define SW_PAD_CTL_A12_A13_A14 IOMUXC_(0x2C8) | ||
350 | #define SW_PAD_CTL_A10_MA10_A11 IOMUXC_(0x2CC) | ||
351 | #define SW_PAD_CTL_A7_A8_A9 IOMUXC_(0x2D0) | ||
352 | #define SW_PAD_CTL_A4_A5_A6 IOMUXC_(0x2D4) | ||
353 | #define SW_PAD_CTL_A1_A2_A3 IOMUXC_(0x2D8) | ||
354 | #define SW_PAD_CTL_VPG0_VPG1_A0 IOMUXC_(0x2DC) | ||
355 | #define SW_PAD_CTL_VSTBY_DVFS0_DVFS1 IOMUXC_(0x2E0) | ||
356 | #define SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL IOMUXC_(0x2E4) | ||
357 | #define SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3 IOMUXC_(0x2E8) | ||
358 | #define SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0 IOMUXC_(0x2EC) | ||
359 | #define SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B IOMUXC_(0x2F0) | ||
360 | #define SW_PAD_CTL_SVEN0_STX0_SRX0 IOMUXC_(0x2F4) | ||
361 | #define SW_PAD_CTL_GPIO3_1_SCLK0_SRST0 IOMUXC_(0x2F8) | ||
362 | #define SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0 IOMUXC_(0x2FC) | ||
363 | #define SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4 IOMUXC_(0x300) | ||
364 | #define SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1 IOMUXC_(0x304) | ||
365 | #define SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST IOMUXC_(0x308) | ||
366 | |||
367 | /* SW_PAD_CTL flags */ | ||
368 | #define SW_PAD_CTL_LOOPBACK (0x1 << 9) /* Route output to input */ | ||
369 | /* Pullup, pulldown and keeper enable */ | 164 | /* Pullup, pulldown and keeper enable */ |
370 | #define SW_PAD_CTL_PUE_PKE (0x3 << 7) | 165 | #define IOMUXC_PAD_PUE_PKE (0x3 << 7) |
371 | #define SW_PAD_CTL_PUE_PKE_DISABLE (0x0 << 7) | 166 | #define IOMUXC_PAD_PUE_PKE_DISABLE (0x0 << 7) |
372 | #define SW_PAD_CTL_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */ | 167 | #define IOMUXC_PAD_PUE_PKE_DISABLE_2 (0x1 << 7) /* Same as 0x0 */ |
373 | #define SW_PAD_CTL_PUE_PKE_KEEPER (0x2 << 7) | 168 | #define IOMUXC_PAD_PUE_PKE_KEEPER (0x2 << 7) |
374 | #define SW_PAD_CTL_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */ | 169 | #define IOMUXC_PAD_PUE_PKE_PULLUPDOWN (0x3 << 7) /* Enb. Pull up or down */ |
375 | /* Pullup/down resistance */ | 170 | /* Pullup/down resistance */ |
376 | #define SW_PAD_CTL_PUS (0x3 << 5) | 171 | #define IOMUXC_PAD_PUS (0x3 << 5) |
377 | #define SW_PAD_CTL_PUS_DOWN_100K (0x0 << 5) | 172 | #define IOMUXC_PAD_PUS_DOWN_100K (0x0 << 5) |
378 | #define SW_PAD_CTL_PUS_UP_100K (0x1 << 5) | 173 | #define IOMUXC_PAD_PUS_UP_100K (0x1 << 5) |
379 | #if 0 /* Completeness */ | 174 | #if 0 /* Completeness */ |
380 | #define SW_PAD_CTL_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */ | 175 | #define IOMUXC_PAD_PUS_UP_47K (0x2 << 5) /* Not in IMX31/L */ |
381 | #define SW_PAD_CTL_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */ | 176 | #define IOMUXC_PAD_PUS_UP_22K (0x3 << 5) /* Not in IMX31/L */ |
382 | #endif | 177 | #endif |
383 | #define SW_PAD_CTL_HYS (0x1 << 4) /* Schmitt trigger input */ | 178 | #define IOMUXC_PAD_HYS (0x1 << 4) /* Schmitt trigger input */ |
384 | #define SW_PAD_CTL_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/ | 179 | #define IOMUXC_PAD_ODE (0x1 << 3) /* Open drain output 0=CMOS pushpull*/ |
385 | #define SW_PAD_CTL_DSE (0x3 << 1) | 180 | #define IOMUXC_PAD_DSE (0x3 << 1) |
386 | #define SW_PAD_CTL_DSE_STD (0x0 << 1) /* Drive strength */ | 181 | #define IOMUXC_PAD_DSE_STD (0x0 << 1) /* Drive strength */ |
387 | #define SW_PAD_CTL_DSE_HIGH (0x1 << 1) | 182 | #define IOMUXC_PAD_DSE_HIGH (0x1 << 1) |
388 | #define SW_PAD_CTL_DSE_MAX (0x2 << 1) | 183 | #define IOMUXC_PAD_DSE_MAX (0x2 << 1) |
389 | #define SW_PAD_CTL_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */ | 184 | #define IOMUXC_PAD_DSE_MAX_2 (0x3 << 1) /* Same as 0x2 */ |
390 | #define SW_PAD_CTL_SRE (0x1 << 0) /* Slew rate, 1=fast */ | 185 | #define IOMUXC_PAD_SRE (0x1 << 0) /* Slew rate, 1=fast */ |
391 | 186 | ||
392 | /* Masks for each IO field */ | 187 | #define IOMUXC_PAD_MASK (0x3ff) |
393 | #define SW_PAD_CTL_IO1 (0x3ff << 0) | ||
394 | #define SW_PAD_CTL_IO2 (0x3ff << 10) | ||
395 | #define SW_PAD_CTL_IO3 (0x3ff << 20) | ||
396 | |||
397 | /* Shift above flags into one of the three fields in each register */ | ||
398 | #define SW_PAD_CTL_IO1_POS (0) | ||
399 | #define SW_PAD_CTL_IO2_POS (10) | ||
400 | #define SW_PAD_CTL_IO3_POS (20) | ||
401 | 188 | ||
402 | /* RNGA */ | 189 | /* RNGA */ |
403 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) | 190 | #define RNGA_CONTROL (*(REG32_PTR_T)(RNGA_BASE_ADDR+0x00)) |
diff --git a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c index d846f4d1d0..f720921fad 100644 --- a/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/fmradio-i2c-gigabeat-s.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "system.h" | 23 | #include "system.h" |
24 | #include "mc13783.h" | 24 | #include "mc13783.h" |
25 | #include "iomuxc-imx31.h" | ||
25 | #include "i2c-imx31.h" | 26 | #include "i2c-imx31.h" |
26 | #include "fmradio_i2c.h" | 27 | #include "fmradio_i2c.h" |
27 | 28 | ||
@@ -48,36 +49,34 @@ void fmradio_i2c_init(void) | |||
48 | 49 | ||
49 | /* open-drain pins - external pullups on PCB. Pullup default but | 50 | /* open-drain pins - external pullups on PCB. Pullup default but |
50 | * disabled */ | 51 | * disabled */ |
51 | imx31_regmod32(&SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1, | 52 | /* RI_DTE1 (I2C2_SCLK) */ |
52 | /* RI_DTE1 (I2C2_SCLK) */ | 53 | iomuxc_set_pad_config(IOMUXC_RI_DTE1, |
53 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | | 54 | IOMUXC_PAD_PUE_PKE_DISABLE | IOMUXC_PAD_PUS_UP_100K | |
54 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO2_POS) | | 55 | IOMUXC_PAD_HYS | IOMUXC_PAD_ODE); |
55 | /* DCD_DTE1 (I2C2_SDA) */ | 56 | /* DCD_DTE1 (I2C2_SDA) */ |
56 | ((SW_PAD_CTL_PUE_PKE_DISABLE | SW_PAD_CTL_PUS_UP_100K | | 57 | iomuxc_set_pad_config(IOMUXC_DCD_DTE1, |
57 | SW_PAD_CTL_HYS | SW_PAD_CTL_ODE) << SW_PAD_CTL_IO1_POS), | 58 | IOMUXC_PAD_PUE_PKE_DISABLE | IOMUXC_PAD_PUS_UP_100K | |
58 | SW_PAD_CTL_IO2 | SW_PAD_CTL_IO1); | 59 | IOMUXC_PAD_HYS | IOMUXC_PAD_ODE); |
60 | |||
59 | /* set outputs to I2C2 */ | 61 | /* set outputs to I2C2 */ |
60 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 62 | /* RI_DTE1 => I2C2_SCLK */ |
61 | /* RI_DTE1 => I2C2_SCLK */ | 63 | iomuxc_set_pin_mux(IOMUXC_RI_DTE1, |
62 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG4_POS) | | 64 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); |
63 | /* DCD_DTE1 => I2C2_SDA */ | 65 | /* DCD_DTE1 => I2C2_SDA */ |
64 | ((SW_MUX_OUT_ALT2 | SW_MUX_IN_ALT2) << SW_MUX_CTL_SIG3_POS), | 66 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
65 | SW_MUX_CTL_SIG4 | SW_MUX_CTL_SIG3); | 67 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); |
66 | } | 68 | } |
67 | 69 | ||
68 | void fmradio_i2c_enable(bool enable) | 70 | void fmradio_i2c_enable(bool enable) |
69 | { | 71 | { |
70 | if (enable) | 72 | if (enable) |
71 | { | 73 | { |
72 | uint32_t io_pin_mux = SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2; | ||
73 | /* place in GPIO mode to hold SDIO low during RESET release, | 74 | /* place in GPIO mode to hold SDIO low during RESET release, |
74 | * SEN1 should be high already (pullup) and GPIO3 left alone */ | 75 | * SEN1 should be high already (pullup) and GPIO3 left alone */ |
75 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ | 76 | imx31_regset32(&GPIO2_GDIR, (1 << 15)); /* SDIO OUT */ |
76 | /* I2C2_SDA => MCU2_15 */ | 77 | /* I2C2_SDA => MCU2_15 */ |
77 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 78 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
78 | (SW_MUX_OUT_GPIO_DR | | 79 | IOMUXC_MUX_OUT_GPIO | IOMUXC_MUX_IN_GPIO); |
79 | SW_MUX_IN_GPIO_PSR_ISR) << SW_MUX_CTL_SIG3_POS, | ||
80 | SW_MUX_CTL_SIG3); | ||
81 | /* enable CLK32KMCU clock */ | 80 | /* enable CLK32KMCU clock */ |
82 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); | 81 | mc13783_set(MC13783_POWER_CONTROL0, MC13783_CLK32KMCUEN); |
83 | /* enable the fm chip (release RESET) */ | 82 | /* enable the fm chip (release RESET) */ |
@@ -85,9 +84,9 @@ void fmradio_i2c_enable(bool enable) | |||
85 | sleep(HZ/100); | 84 | sleep(HZ/100); |
86 | /* busmode should be selected - OK to release SDIO */ | 85 | /* busmode should be selected - OK to release SDIO */ |
87 | imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ | 86 | imx31_regclr32(&GPIO2_GDIR, (1 << 15)); /* SDIO IN */ |
88 | /* restore pin mux (DCD_DTE1 => I2C2_SDA) */ | 87 | /* restore pin mux (MCU2_15 => I2C2_SDA) */ |
89 | imx31_regmod32(&SW_MUX_CTL_RI_DTE1_DCD_DTE1_DTR_DCE2_RXD2, | 88 | iomuxc_set_pin_mux(IOMUXC_DCD_DTE1, |
90 | io_pin_mux, SW_MUX_CTL_SIG3); | 89 | IOMUXC_MUX_OUT_ALT2 | IOMUXC_MUX_IN_ALT2); |
91 | /* the si4700 is the only thing connected to i2c2 so | 90 | /* the si4700 is the only thing connected to i2c2 so |
92 | we can diable the i2c module when not in use */ | 91 | we can diable the i2c module when not in use */ |
93 | i2c_enable_node(&si4700_i2c_node, true); | 92 | i2c_enable_node(&si4700_i2c_node, true); |
diff --git a/firmware/target/arm/imx31/iomuxc-imx31.c b/firmware/target/arm/imx31/iomuxc-imx31.c new file mode 100644 index 0000000000..876b8b2a9c --- /dev/null +++ b/firmware/target/arm/imx31/iomuxc-imx31.c | |||
@@ -0,0 +1,50 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (c) 2010 Michael Sevakis | ||
11 | * | ||
12 | * i.MX31 IOMUXC helper routines | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #include "config.h" | ||
24 | #include "system.h" | ||
25 | #include "iomuxc-imx31.h" | ||
26 | |||
27 | |||
28 | /* Set the pin multiplexing configuration (functional, GPIO, etc.) */ | ||
29 | void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, | ||
30 | unsigned long mux) | ||
31 | { | ||
32 | unsigned long index = pin / 4; | ||
33 | unsigned int shift = 8*(pin % 4); | ||
34 | |||
35 | imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index, | ||
36 | mux << shift, IOMUXC_MUX_MASK << shift); | ||
37 | } | ||
38 | |||
39 | |||
40 | /* Set the pin pad configuration (keeper, drive strength, etc.) */ | ||
41 | void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, | ||
42 | unsigned long config) | ||
43 | { | ||
44 | unsigned long padoffs = pin + 2; | ||
45 | unsigned long index = padoffs / 3; | ||
46 | unsigned int shift = 10*(padoffs % 3); | ||
47 | |||
48 | imx31_regmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index, | ||
49 | config << shift, IOMUXC_PAD_MASK << shift); | ||
50 | } | ||
diff --git a/firmware/target/arm/imx31/iomuxc-imx31.h b/firmware/target/arm/imx31/iomuxc-imx31.h new file mode 100644 index 0000000000..198b55d774 --- /dev/null +++ b/firmware/target/arm/imx31/iomuxc-imx31.h | |||
@@ -0,0 +1,364 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (c) 2010 Michael Sevakis | ||
11 | * | ||
12 | * i.MX31 IOMUXC helper routines | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or | ||
15 | * modify it under the terms of the GNU General Public License | ||
16 | * as published by the Free Software Foundation; either version 2 | ||
17 | * of the License, or (at your option) any later version. | ||
18 | * | ||
19 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
20 | * KIND, either express or implied. | ||
21 | * | ||
22 | ****************************************************************************/ | ||
23 | #ifndef _IOMUXC_IMX31_H_ | ||
24 | #define _IOMUXC_IMX31_H_ | ||
25 | |||
26 | enum IMX31_IOMUXC_PINS | ||
27 | { | ||
28 | IOMUXC_TTM_PAD = 0, | ||
29 | IOMUXC_CSPI3_SPI_RDY = 1, | ||
30 | IOMUXC_CSPI3_SCLK = 2, | ||
31 | IOMUXC_CSPI3_MISO = 3, | ||
32 | IOMUXC_CSPI3_MOSI = 4, | ||
33 | IOMUXC_CLKSS = 5, | ||
34 | IOMUXC_CE_CONTROL = 6, | ||
35 | IOMUXC_ATA_RST_B = 7, | ||
36 | IOMUXC_ATA_DMACK = 8, | ||
37 | IOMUXC_ATA_DIOW = 9, | ||
38 | IOMUXC_ATA_DIOR = 10, | ||
39 | IOMUXC_ATA_CS1 = 11, | ||
40 | IOMUXC_ATA_CS0 = 12, | ||
41 | IOMUXC_SD1_DATA3 = 13, | ||
42 | IOMUXC_SD1_DATA2 = 14, | ||
43 | IOMUXC_SD1_DATA1 = 15, | ||
44 | IOMUXC_SD1_DATA0 = 16, | ||
45 | IOMUXC_SD1_CLK = 17, | ||
46 | IOMUXC_SD1_CMD = 18, | ||
47 | IOMUXC_D3_SPL = 19, | ||
48 | IOMUXC_D3_CLS = 20, | ||
49 | IOMUXC_D3_REV = 21, | ||
50 | IOMUXC_CONTRAST = 22, | ||
51 | IOMUXC_VSYNC3 = 23, | ||
52 | IOMUXC_READ = 24, | ||
53 | IOMUXC_WRITE = 25, | ||
54 | IOMUXC_PAR_RS = 26, | ||
55 | IOMUXC_SER_RS = 27, | ||
56 | IOMUXC_LCS1 = 28, | ||
57 | IOMUXC_LCS0 = 29, | ||
58 | IOMUXC_SD_D_CLK = 30, | ||
59 | IOMUXC_SD_D_IO = 31, | ||
60 | IOMUXC_SD_D_I = 32, | ||
61 | IOMUXC_DRDY0 = 33, | ||
62 | IOMUXC_FPSHIFT = 34, | ||
63 | IOMUXC_HSYNC = 35, | ||
64 | IOMUXC_VSYNC0 = 36, | ||
65 | IOMUXC_LD17 = 37, | ||
66 | IOMUXC_LD16 = 38, | ||
67 | IOMUXC_LD15 = 39, | ||
68 | IOMUXC_LD14 = 40, | ||
69 | IOMUXC_LD13 = 41, | ||
70 | IOMUXC_LD12 = 42, | ||
71 | IOMUXC_LD11 = 43, | ||
72 | IOMUXC_LD10 = 44, | ||
73 | IOMUXC_LD9 = 45, | ||
74 | IOMUXC_LD8 = 46, | ||
75 | IOMUXC_LD7 = 47, | ||
76 | IOMUXC_LD6 = 48, | ||
77 | IOMUXC_LD5 = 49, | ||
78 | IOMUXC_LD4 = 50, | ||
79 | IOMUXC_LD3 = 51, | ||
80 | IOMUXC_LD2 = 52, | ||
81 | IOMUXC_LD1 = 53, | ||
82 | IOMUXC_LD0 = 54, | ||
83 | IOMUXC_USBH2_DATA1 = 55, | ||
84 | IOMUXC_USBH2_DATA0 = 56, | ||
85 | IOMUXC_USBH2_NXT = 57, | ||
86 | IOMUXC_USBH2_STP = 58, | ||
87 | IOMUXC_USBH2_DIR = 59, | ||
88 | IOMUXC_USBH2_CLK = 60, | ||
89 | IOMUXC_USBOTG_DATA7 = 61, | ||
90 | IOMUXC_USBOTG_DATA6 = 62, | ||
91 | IOMUXC_USBOTG_DATA5 = 63, | ||
92 | IOMUXC_USBOTG_DATA4 = 64, | ||
93 | IOMUXC_USBOTG_DATA3 = 65, | ||
94 | IOMUXC_USBOTG_DATA2 = 66, | ||
95 | IOMUXC_USBOTG_DATA1 = 67, | ||
96 | IOMUXC_USBOTG_DATA0 = 68, | ||
97 | IOMUXC_USBOTG_NXT = 69, | ||
98 | IOMUXC_USBOTG_STP = 70, | ||
99 | IOMUXC_USBOTG_DIR = 71, | ||
100 | IOMUXC_USBOTG_CLK = 72, | ||
101 | IOMUXC_USB_BYP = 73, | ||
102 | IOMUXC_USB_OC = 74, | ||
103 | IOMUXC_USB_PWR = 75, | ||
104 | IOMUXC_SJC_MOD = 76, | ||
105 | IOMUXC_DE_B = 77, | ||
106 | IOMUXC_TRSTB = 78, | ||
107 | IOMUXC_TDO = 79, | ||
108 | IOMUXC_TDI = 80, | ||
109 | IOMUXC_TMS = 81, | ||
110 | IOMUXC_TCK = 82, | ||
111 | IOMUXC_RTCK = 83, | ||
112 | IOMUXC_KEY_COL7 = 84, | ||
113 | IOMUXC_KEY_COL6 = 85, | ||
114 | IOMUXC_KEY_COL5 = 86, | ||
115 | IOMUXC_KEY_COL4 = 87, | ||
116 | IOMUXC_KEY_COL3 = 88, | ||
117 | IOMUXC_KEY_COL2 = 89, | ||
118 | IOMUXC_KEY_COL1 = 90, | ||
119 | IOMUXC_KEY_COL0 = 91, | ||
120 | IOMUXC_KEY_ROW7 = 92, | ||
121 | IOMUXC_KEY_ROW6 = 93, | ||
122 | IOMUXC_KEY_ROW5 = 94, | ||
123 | IOMUXC_KEY_ROW4 = 95, | ||
124 | IOMUXC_KEY_ROW3 = 96, | ||
125 | IOMUXC_KEY_ROW2 = 97, | ||
126 | IOMUXC_KEY_ROW1 = 98, | ||
127 | IOMUXC_KEY_ROW0 = 99, | ||
128 | IOMUXC_BATT_LINE = 100, | ||
129 | IOMUXC_CTS2 = 101, | ||
130 | IOMUXC_RTS2 = 102, | ||
131 | IOMUXC_TXD2 = 103, | ||
132 | IOMUXC_RXD2 = 104, | ||
133 | IOMUXC_DTR_DCE2 = 105, | ||
134 | IOMUXC_DCD_DTE1 = 106, | ||
135 | IOMUXC_RI_DTE1 = 107, | ||
136 | IOMUXC_DSR_DTE1 = 108, | ||
137 | IOMUXC_DTR_DTE1 = 109, | ||
138 | IOMUXC_DCD_DCE1 = 110, | ||
139 | IOMUXC_RI_DCE1 = 111, | ||
140 | IOMUXC_DSR_DCE1 = 112, | ||
141 | IOMUXC_DTR_DCE1 = 113, | ||
142 | IOMUXC_CTS1 = 114, | ||
143 | IOMUXC_RTS1 = 115, | ||
144 | IOMUXC_TXD1 = 116, | ||
145 | IOMUXC_RXD1 = 117, | ||
146 | IOMUXC_CSPI2_SPI_RDY = 118, | ||
147 | IOMUXC_CSPI2_SCLK = 119, | ||
148 | IOMUXC_CSPI2_SS2 = 120, | ||
149 | IOMUXC_CSPI2_SS1 = 121, | ||
150 | IOMUXC_CSPI2_SS0 = 122, | ||
151 | IOMUXC_CSPI2_MISO = 123, | ||
152 | IOMUXC_CSPI2_MOSI = 124, | ||
153 | IOMUXC_CSPI1_SPI_RDY = 125, | ||
154 | IOMUXC_CSPI1_SCLK = 126, | ||
155 | IOMUXC_CSPI1_SS2 = 127, | ||
156 | IOMUXC_CSPI1_SS1 = 128, | ||
157 | IOMUXC_CSPI1_SS0 = 129, | ||
158 | IOMUXC_CSPI1_MISO = 130, | ||
159 | IOMUXC_CSPI1_MOSI = 131, | ||
160 | IOMUXC_SFS6 = 132, | ||
161 | IOMUXC_SCK6 = 133, | ||
162 | IOMUXC_SRXD6 = 134, | ||
163 | IOMUXC_STXD6 = 135, | ||
164 | IOMUXC_SFS5 = 136, | ||
165 | IOMUXC_SCK5 = 137, | ||
166 | IOMUXC_SRXD5 = 138, | ||
167 | IOMUXC_STXD5 = 139, | ||
168 | IOMUXC_SFS4 = 140, | ||
169 | IOMUXC_SCK4 = 141, | ||
170 | IOMUXC_SRXD4 = 142, | ||
171 | IOMUXC_STXD4 = 143, | ||
172 | IOMUXC_SFS3 = 144, | ||
173 | IOMUXC_SCK3 = 145, | ||
174 | IOMUXC_SRXD3 = 146, | ||
175 | IOMUXC_STXD3 = 147, | ||
176 | IOMUXC_I2C_DAT = 148, | ||
177 | IOMUXC_I2C_CLK = 149, | ||
178 | IOMUXC_CSI_PIXCLK = 150, | ||
179 | IOMUXC_CSI_HSYNC = 151, | ||
180 | IOMUXC_CSI_VSYNC = 152, | ||
181 | IOMUXC_CSI_MCLK = 153, | ||
182 | IOMUXC_CSI_D15 = 154, | ||
183 | IOMUXC_CSI_D14 = 155, | ||
184 | IOMUXC_CSI_D13 = 156, | ||
185 | IOMUXC_CSI_D12 = 157, | ||
186 | IOMUXC_CSI_D11 = 158, | ||
187 | IOMUXC_CSI_D10 = 159, | ||
188 | IOMUXC_CSI_D9 = 160, | ||
189 | IOMUXC_CSI_D8 = 161, | ||
190 | IOMUXC_CSI_D7 = 162, | ||
191 | IOMUXC_CSI_D6 = 163, | ||
192 | IOMUXC_CSI_D5 = 164, | ||
193 | IOMUXC_CSI_D4 = 165, | ||
194 | IOMUXC_M_GRANT = 166, | ||
195 | IOMUXC_M_REQUEST = 167, | ||
196 | IOMUXC_PC_POE = 168, | ||
197 | IOMUXC_PC_RW_B = 169, | ||
198 | IOMUXC_IOIS16 = 170, | ||
199 | IOMUXC_PC_RST = 171, | ||
200 | IOMUXC_PC_BVD2 = 172, | ||
201 | IOMUXC_PC_BVD1 = 173, | ||
202 | IOMUXC_PC_VS2 = 174, | ||
203 | IOMUXC_PC_VS1 = 175, | ||
204 | IOMUXC_PC_PWRON = 176, | ||
205 | IOMUXC_PC_READY = 177, | ||
206 | IOMUXC_PC_WAIT_B = 178, | ||
207 | IOMUXC_PC_CD2_B = 179, | ||
208 | IOMUXC_PC_CD1_B = 180, | ||
209 | IOMUXC_D0 = 181, | ||
210 | IOMUXC_D1 = 182, | ||
211 | IOMUXC_D2 = 183, | ||
212 | IOMUXC_D3 = 184, | ||
213 | IOMUXC_D4 = 185, | ||
214 | IOMUXC_D5 = 186, | ||
215 | IOMUXC_D6 = 187, | ||
216 | IOMUXC_D7 = 188, | ||
217 | IOMUXC_D8 = 189, | ||
218 | IOMUXC_D9 = 190, | ||
219 | IOMUXC_D10 = 191, | ||
220 | IOMUXC_D11 = 192, | ||
221 | IOMUXC_D12 = 193, | ||
222 | IOMUXC_D13 = 194, | ||
223 | IOMUXC_D14 = 195, | ||
224 | IOMUXC_D15 = 196, | ||
225 | IOMUXC_NFRB = 197, | ||
226 | IOMUXC_NFCE_B = 198, | ||
227 | IOMUXC_NFWP_B = 199, | ||
228 | IOMUXC_NFCLE = 200, | ||
229 | IOMUXC_NFALE = 201, | ||
230 | IOMUXC_NFRE_B = 202, | ||
231 | IOMUXC_NFWE_B = 203, | ||
232 | IOMUXC_SDQS3 = 204, | ||
233 | IOMUXC_SDQS2 = 205, | ||
234 | IOMUXC_SDQS1 = 206, | ||
235 | IOMUXC_SDQS0 = 207, | ||
236 | IOMUXC_RESERVED0 = 208, | ||
237 | IOMUXC_SDCLK = 209, | ||
238 | IOMUXC_SDCKE1 = 210, | ||
239 | IOMUXC_SDCKE0 = 211, | ||
240 | IOMUXC_SDWE = 212, | ||
241 | IOMUXC_CAS = 213, | ||
242 | IOMUXC_RAS = 214, | ||
243 | IOMUXC_RW = 215, | ||
244 | IOMUXC_BCLK = 216, | ||
245 | IOMUXC_LBA = 217, | ||
246 | IOMUXC_ECB = 218, | ||
247 | IOMUXC_CS5 = 219, | ||
248 | IOMUXC_CS4 = 220, | ||
249 | IOMUXC_CS3 = 221, | ||
250 | IOMUXC_CS2 = 222, | ||
251 | IOMUXC_CS1 = 223, | ||
252 | IOMUXC_CS0 = 224, | ||
253 | IOMUXC_OE = 225, | ||
254 | IOMUXC_EB1 = 226, | ||
255 | IOMUXC_EB0 = 227, | ||
256 | IOMUXC_DQM3 = 228, | ||
257 | IOMUXC_DQM2 = 229, | ||
258 | IOMUXC_DQM1 = 230, | ||
259 | IOMUXC_DQM0 = 231, | ||
260 | IOMUXC_SD31 = 232, | ||
261 | IOMUXC_SD30 = 233, | ||
262 | IOMUXC_SD29 = 234, | ||
263 | IOMUXC_SD28 = 235, | ||
264 | IOMUXC_SD27 = 236, | ||
265 | IOMUXC_SD26 = 237, | ||
266 | IOMUXC_SD25 = 238, | ||
267 | IOMUXC_SD24 = 239, | ||
268 | IOMUXC_SD23 = 240, | ||
269 | IOMUXC_SD22 = 241, | ||
270 | IOMUXC_SD21 = 242, | ||
271 | IOMUXC_SD20 = 243, | ||
272 | IOMUXC_SD19 = 244, | ||
273 | IOMUXC_SD18 = 245, | ||
274 | IOMUXC_SD17 = 246, | ||
275 | IOMUXC_SD16 = 247, | ||
276 | IOMUXC_SD15 = 248, | ||
277 | IOMUXC_SD14 = 249, | ||
278 | IOMUXC_SD13 = 250, | ||
279 | IOMUXC_SD12 = 251, | ||
280 | IOMUXC_SD11 = 252, | ||
281 | IOMUXC_SD10 = 253, | ||
282 | IOMUXC_SD9 = 254, | ||
283 | IOMUXC_SD8 = 255, | ||
284 | IOMUXC_SD7 = 256, | ||
285 | IOMUXC_SD6 = 257, | ||
286 | IOMUXC_SD5 = 258, | ||
287 | IOMUXC_SD4 = 259, | ||
288 | IOMUXC_SD3 = 260, | ||
289 | IOMUXC_SD2 = 261, | ||
290 | IOMUXC_SD1 = 262, | ||
291 | IOMUXC_SD0 = 263, | ||
292 | IOMUXC_SDBA0 = 264, | ||
293 | IOMUXC_SDBA1 = 265, | ||
294 | IOMUXC_A25 = 266, | ||
295 | IOMUXC_A24 = 267, | ||
296 | IOMUXC_A23 = 268, | ||
297 | IOMUXC_A22 = 269, | ||
298 | IOMUXC_A21 = 270, | ||
299 | IOMUXC_A20 = 271, | ||
300 | IOMUXC_A19 = 272, | ||
301 | IOMUXC_A18 = 273, | ||
302 | IOMUXC_A17 = 274, | ||
303 | IOMUXC_A16 = 275, | ||
304 | IOMUXC_A15 = 276, | ||
305 | IOMUXC_A14 = 277, | ||
306 | IOMUXC_A13 = 278, | ||
307 | IOMUXC_A12 = 279, | ||
308 | IOMUXC_A11 = 280, | ||
309 | IOMUXC_MA10 = 281, | ||
310 | IOMUXC_A10 = 282, | ||
311 | IOMUXC_A9 = 283, | ||
312 | IOMUXC_A8 = 284, | ||
313 | IOMUXC_A7 = 285, | ||
314 | IOMUXC_A6 = 286, | ||
315 | IOMUXC_A5 = 287, | ||
316 | IOMUXC_A4 = 288, | ||
317 | IOMUXC_A3 = 289, | ||
318 | IOMUXC_A2 = 290, | ||
319 | IOMUXC_A1 = 291, | ||
320 | IOMUXC_A0 = 292, | ||
321 | IOMUXC_VPG1 = 293, | ||
322 | IOMUXC_VPG0 = 294, | ||
323 | IOMUXC_DVFS1 = 295, | ||
324 | IOMUXC_DVFS0 = 296, | ||
325 | IOMUXC_VSTBY = 297, | ||
326 | IOMUXC_POWER_FAIL = 298, | ||
327 | IOMUXC_CKIL = 299, | ||
328 | IOMUXC_BOOT_MODE4 = 300, | ||
329 | IOMUXC_BOOT_MODE3 = 301, | ||
330 | IOMUXC_BOOT_MODE2 = 302, | ||
331 | IOMUXC_BOOT_MODE1 = 303, | ||
332 | IOMUXC_BOOT_MODE0 = 304, | ||
333 | IOMUXC_CLKO = 305, | ||
334 | IOMUXC_POR_B = 306, | ||
335 | IOMUXC_RESET_IN_B = 307, | ||
336 | IOMUXC_CKIH = 308, | ||
337 | IOMUXC_SIMPD0 = 309, | ||
338 | IOMUXC_SRX0 = 310, | ||
339 | IOMUXC_STX0 = 311, | ||
340 | IOMUXC_SVEN0 = 312, | ||
341 | IOMUXC_SRST0 = 313, | ||
342 | IOMUXC_SCLK0 = 314, | ||
343 | IOMUXC_GPIO3_1 = 315, | ||
344 | IOMUXC_GPIO3_0 = 316, | ||
345 | IOMUXC_GPIO1_6 = 317, | ||
346 | IOMUXC_GPIO1_5 = 318, | ||
347 | IOMUXC_GPIO1_4 = 319, | ||
348 | IOMUXC_GPIO1_3 = 320, | ||
349 | IOMUXC_GPIO1_2 = 321, | ||
350 | IOMUXC_GPIO1_1 = 322, | ||
351 | IOMUXC_GPIO1_0 = 323, | ||
352 | IOMUXC_PWMO = 324, | ||
353 | IOMUXC_WATCHDOG_RST = 325, | ||
354 | IOMUXC_COMPARE = 326, | ||
355 | IOMUXC_CAPTURE = 327, | ||
356 | }; | ||
357 | |||
358 | /* Set the pin multiplexing configuration (functional, GPIO, etc.) */ | ||
359 | void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, unsigned long mux); | ||
360 | |||
361 | /* Set the pin pad configuration (keeper, drive strength, etc.) */ | ||
362 | void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, unsigned long config); | ||
363 | |||
364 | #endif /* _IOMUXC_IMX31_H_ */ | ||