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author | Marcin Bukat <marcin.bukat@gmail.com> | 2011-07-19 06:49:03 +0000 |
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committer | Marcin Bukat <marcin.bukat@gmail.com> | 2011-07-19 06:49:03 +0000 |
commit | 5d9b23016852af99d285521f71a23ddea99ae7ee (patch) | |
tree | 7177428091eb7224e9805a0f10a8c9effea63969 /firmware | |
parent | f1c7fba5a474ebdfd1e162459df1a513911da1b7 (diff) | |
download | rockbox-5d9b23016852af99d285521f71a23ddea99ae7ee.tar.gz rockbox-5d9b23016852af99d285521f71a23ddea99ae7ee.zip |
rk27xx - implement cache_commit_discard(). Cache is still not enabled in crt0.S
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30167 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/rk27xx.h | 5 | ||||
-rw-r--r-- | firmware/target/arm/rk27xx/system-rk27xx.c | 16 | ||||
-rw-r--r-- | firmware/target/arm/rk27xx/system-target.h | 4 |
3 files changed, 24 insertions, 1 deletions
diff --git a/firmware/export/rk27xx.h b/firmware/export/rk27xx.h index a5cd396a33..7ada367627 100644 --- a/firmware/export/rk27xx.h +++ b/firmware/export/rk27xx.h | |||
@@ -7,6 +7,9 @@ | |||
7 | #define FLASH_BANK0 0x10000000 | 7 | #define FLASH_BANK0 0x10000000 |
8 | #define FLASH_BANK1 0x11000000 | 8 | #define FLASH_BANK1 0x11000000 |
9 | 9 | ||
10 | #define USB_NUM_ENDPOINTS 16 | ||
11 | #define USB_DEVBSS_ATTR | ||
12 | |||
10 | /* Timers */ | 13 | /* Timers */ |
11 | #define APB0_TIMER (ARM_BUS0_BASE + 0x00000000) | 14 | #define APB0_TIMER (ARM_BUS0_BASE + 0x00000000) |
12 | #define TMR0LR (*(volatile unsigned long *)(APB0_TIMER + 0x00)) | 15 | #define TMR0LR (*(volatile unsigned long *)(APB0_TIMER + 0x00)) |
@@ -1006,7 +1009,7 @@ | |||
1006 | #define DMACHEN_CH3 (0x101<<3) | 1009 | #define DMACHEN_CH3 (0x101<<3) |
1007 | 1010 | ||
1008 | /* ARM7 cache controller */ | 1011 | /* ARM7 cache controller */ |
1009 | #define ARM_CACHE_CNTRL 0xEFFF0000 | 1012 | #define ARM_CACHE_CTRL 0xEFFF0000 |
1010 | #define DEVID (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x00)) | 1013 | #define DEVID (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x00)) |
1011 | #define CACHEOP (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x04)) | 1014 | #define CACHEOP (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x04)) |
1012 | #define CACHELKDN (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x08)) | 1015 | #define CACHELKDN (*(volatile unsigned long *)(ARM_CACHE_CTRL + 0x08)) |
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index 724273b61a..1459770b94 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c | |||
@@ -163,3 +163,19 @@ void udelay(unsigned usecs) | |||
163 | ); | 163 | ); |
164 | } | 164 | } |
165 | 165 | ||
166 | void cpucache_commit_discard(void) | ||
167 | { | ||
168 | /* invalidate cache way 0 */ | ||
169 | CACHEOP = 0x02; | ||
170 | |||
171 | /* wait for invalidate process to complete */ | ||
172 | while (CACHEOP & 0x01); | ||
173 | |||
174 | /* invalidate cache way 1 */ | ||
175 | CACHEOP = 0x80000002; | ||
176 | |||
177 | /* wait for invalidate process to complete */ | ||
178 | while (CACHEOP & 0x01); | ||
179 | } | ||
180 | |||
181 | void cpucache_invalidate(void) __attribute__((alias("cpucache_commit_discard"))); | ||
diff --git a/firmware/target/arm/rk27xx/system-target.h b/firmware/target/arm/rk27xx/system-target.h index fb904091b1..7fcf470ced 100644 --- a/firmware/target/arm/rk27xx/system-target.h +++ b/firmware/target/arm/rk27xx/system-target.h | |||
@@ -38,6 +38,10 @@ static inline void core_sleep(void) | |||
38 | SCU_CPUPD = 0xdeedbabe; | 38 | SCU_CPUPD = 0xdeedbabe; |
39 | } | 39 | } |
40 | 40 | ||
41 | #define HAVE_CPUCACHE_COMMIT_DISCARD | ||
42 | /* deprecated alias */ | ||
43 | #define HAVE_CPUCACHE_INVALIDATE | ||
44 | |||
41 | #define CPUFREQ_NORMAL 200000000 | 45 | #define CPUFREQ_NORMAL 200000000 |
42 | #define CPUFREQ_MAX 200000000 | 46 | #define CPUFREQ_MAX 200000000 |
43 | 47 | ||