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author | Rafaël Carré <rafael.carre@gmail.com> | 2011-12-31 21:15:10 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2011-12-31 21:15:10 +0000 |
commit | 18bee1bafb7ce4cb7610a491c12c2d41939a2c2f (patch) | |
tree | ca60266da8bdb69a1d62bce76ecb0a1d7e989afc /firmware | |
parent | 12b70597a6112224c40b8e774809c7de49b4fdc3 (diff) | |
download | rockbox-18bee1bafb7ce4cb7610a491c12c2d41939a2c2f.tar.gz rockbox-18bee1bafb7ce4cb7610a491c12c2d41939a2c2f.zip |
usb-drv-as3525v2.h: remove
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31507 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/as3525v2.h | 39 | ||||
-rw-r--r-- | firmware/export/usb-s3c6400x.h | 8 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.c | 1 | ||||
-rw-r--r-- | firmware/target/arm/as3525/usb-drv-as3525v2.h | 75 |
4 files changed, 47 insertions, 76 deletions
diff --git a/firmware/export/as3525v2.h b/firmware/export/as3525v2.h index 4c571f2a22..3778ff7785 100644 --- a/firmware/export/as3525v2.h +++ b/firmware/export/as3525v2.h | |||
@@ -45,4 +45,43 @@ | |||
45 | #undef USB_DEVBSS_ATTR | 45 | #undef USB_DEVBSS_ATTR |
46 | #define USB_DEVBSS_ATTR __attribute__((aligned(32))) | 46 | #define USB_DEVBSS_ATTR __attribute__((aligned(32))) |
47 | 47 | ||
48 | #define USBPHY_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset)) | ||
49 | |||
50 | /** User HW Config1 Register */ | ||
51 | #define GHWCFG1 USBPHY_REG(0x044) | ||
52 | #define GHWCFG1_epdir_bitp(ep) (2 * (ep)) | ||
53 | #define GHWCFG1_epdir_bits 0x3 | ||
54 | #define GHWCFG1_EPDIR_BIDIR 0 | ||
55 | #define GHWCFG1_EPDIR_IN 1 | ||
56 | #define GHWCFG1_EPDIR_OUT 2 | ||
57 | |||
58 | /** User HW Config2 Register */ | ||
59 | #define GHWCFG2 USBPHY_REG(0x048) | ||
60 | #define GHWCFG2_arch_bitp 3 /** Architecture */ | ||
61 | #define GHWCFG2_arch_bits 0x3 | ||
62 | #define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */ | ||
63 | #define GHWCFG2_hs_phy_type_bits 0x3 | ||
64 | #define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */ | ||
65 | #define GHWCFG2_fs_phy_type_bits 0x3 | ||
66 | #define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */ | ||
67 | #define GHWCFG2_num_ep_bits 0xf | ||
68 | #define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */ | ||
69 | /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */ | ||
70 | #define GHWCFG2_PHY_TYPE_UNSUPPORTED 0 | ||
71 | #define GHWCFG2_PHY_TYPE_UTMI 1 | ||
72 | #define GHWCFG2_ARCH_INTERNAL_DMA 2 | ||
73 | |||
74 | /** User HW Config3 Register */ | ||
75 | #define GHWCFG3 USBPHY_REG(0x04C) | ||
76 | #define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */ | ||
77 | #define GHWCFG3_dfifo_len_bits 0xffff | ||
78 | |||
79 | /** User HW Config4 Register */ | ||
80 | #define GHWCFG4 USBPHY_REG(0x050) | ||
81 | #define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */ | ||
82 | #define GHWCFG4_utmi_phy_data_width_bits 0x3 | ||
83 | #define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */ | ||
84 | #define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ | ||
85 | #define GHWCFG4_num_in_ep_bits 0xf | ||
86 | |||
48 | #endif /* __AS3525V2_H__ */ | 87 | #endif /* __AS3525V2_H__ */ |
diff --git a/firmware/export/usb-s3c6400x.h b/firmware/export/usb-s3c6400x.h index 4c5f57e5ad..165ab4e461 100644 --- a/firmware/export/usb-s3c6400x.h +++ b/firmware/export/usb-s3c6400x.h | |||
@@ -480,6 +480,14 @@ | |||
480 | /** Device Endpoint (ep) DMA Address Register */ | 480 | /** Device Endpoint (ep) DMA Address Register */ |
481 | #define DEPDMA(x,out) (*((const void* volatile*)(OTGBASE + 0x914 + (0x200 * (!!out)) + 0x20 * (x)))) | 481 | #define DEPDMA(x,out) (*((const void* volatile*)(OTGBASE + 0x914 + (0x200 * (!!out)) + 0x20 * (x)))) |
482 | 482 | ||
483 | #if 0 /* Those are present in as3525v2, not s5l870x */ | ||
484 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ | ||
485 | #define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x)))) | ||
486 | |||
487 | /** Device OUT Endpoint (ep) Frame number Register */ | ||
488 | #define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x)))) | ||
489 | #endif | ||
490 | |||
483 | /* Power and Clock Gating Register */ | 491 | /* Power and Clock Gating Register */ |
484 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) | 492 | #define PCGCCTL (*((uint32_t volatile*)(OTGBASE + 0xE00))) |
485 | 493 | ||
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.c b/firmware/target/arm/as3525/usb-drv-as3525v2.c index c9d687f910..e9a2ca8178 100644 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.c +++ b/firmware/target/arm/as3525/usb-drv-as3525v2.c | |||
@@ -33,7 +33,6 @@ | |||
33 | #include "system.h" | 33 | #include "system.h" |
34 | //#define LOGF_ENABLE | 34 | //#define LOGF_ENABLE |
35 | #include "logf.h" | 35 | #include "logf.h" |
36 | #include "usb-drv-as3525v2.h" | ||
37 | #include "usb_core.h" | 36 | #include "usb_core.h" |
38 | 37 | ||
39 | static const uint8_t in_ep_list[] = {0, 1, 3, 5}; | 38 | static const uint8_t in_ep_list[] = {0, 1, 3, 5}; |
diff --git a/firmware/target/arm/as3525/usb-drv-as3525v2.h b/firmware/target/arm/as3525/usb-drv-as3525v2.h deleted file mode 100644 index 7f45f52014..0000000000 --- a/firmware/target/arm/as3525/usb-drv-as3525v2.h +++ /dev/null | |||
@@ -1,75 +0,0 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright © 2010 Amaury Pouly | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | #ifndef __USB_DRV_AS3525v2_H__ | ||
22 | #define __USB_DRV_AS3525v2_H__ | ||
23 | |||
24 | #include "as3525v2.h" | ||
25 | #include "usb-s3c6400x.h" | ||
26 | |||
27 | /** | ||
28 | * Registers not present in usb-s3c6400 | ||
29 | */ | ||
30 | #define BASE_REG(offset) (*(volatile uint32_t*)(OTGBASE + offset)) | ||
31 | |||
32 | /** User HW Config1 Register */ | ||
33 | #define GHWCFG1 BASE_REG(0x044) | ||
34 | #define GHWCFG1_epdir_bitp(ep) (2 * (ep)) | ||
35 | #define GHWCFG1_epdir_bits 0x3 | ||
36 | #define GHWCFG1_EPDIR_BIDIR 0 | ||
37 | #define GHWCFG1_EPDIR_IN 1 | ||
38 | #define GHWCFG1_EPDIR_OUT 2 | ||
39 | |||
40 | /** User HW Config2 Register */ | ||
41 | #define GHWCFG2 BASE_REG(0x048) | ||
42 | #define GHWCFG2_arch_bitp 3 /** Architecture */ | ||
43 | #define GHWCFG2_arch_bits 0x3 | ||
44 | #define GHWCFG2_hs_phy_type_bitp 6 /** High speed PHY type */ | ||
45 | #define GHWCFG2_hs_phy_type_bits 0x3 | ||
46 | #define GHWCFG2_fs_phy_type_bitp 8 /** Full speed PHY type */ | ||
47 | #define GHWCFG2_fs_phy_type_bits 0x3 | ||
48 | #define GHWCFG2_num_ep_bitp 10 /** Number of endpoints */ | ||
49 | #define GHWCFG2_num_ep_bits 0xf | ||
50 | #define GHWCFG2_dyn_fifo (1 << 19) /** Dynamic FIFO */ | ||
51 | /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */ | ||
52 | #define GHWCFG2_PHY_TYPE_UNSUPPORTED 0 | ||
53 | #define GHWCFG2_PHY_TYPE_UTMI 1 | ||
54 | #define GHWCFG2_ARCH_INTERNAL_DMA 2 | ||
55 | |||
56 | /** User HW Config3 Register */ | ||
57 | #define GHWCFG3 BASE_REG(0x04C) | ||
58 | #define GHWCFG3_dfifo_len_bitp 16 /** Total fifo size */ | ||
59 | #define GHWCFG3_dfifo_len_bits 0xffff | ||
60 | |||
61 | /** User HW Config4 Register */ | ||
62 | #define GHWCFG4 BASE_REG(0x050) | ||
63 | #define GHWCFG4_utmi_phy_data_width_bitp 14 /** UTMI+ data bus width */ | ||
64 | #define GHWCFG4_utmi_phy_data_width_bits 0x3 | ||
65 | #define GHWCFG4_ded_fifo_en (1 << 25) /** Dedicated Tx FIFOs */ | ||
66 | #define GHWCFG4_num_in_ep_bitp 26 /** Number of IN endpoints */ | ||
67 | #define GHWCFG4_num_in_ep_bits 0xf | ||
68 | |||
69 | /** Device IN Endpoint (ep) Transmit FIFO Status Register */ | ||
70 | #define DTXFSTS(ep) (*((const void* volatile*)(OTGBASE + 0x918 + 0x20 * (x)))) | ||
71 | |||
72 | /** Device OUT Endpoint (ep) Frame number Register */ | ||
73 | #define DOEPFN(ep) (*((const void* volatile*)(OTGBASE + 0xB04 + 0x20 * (x)))) | ||
74 | |||
75 | #endif /* __USB_DRV_AS3525v2_H__ */ | ||