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author | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 15:58:36 +0200 |
---|---|---|
committer | Amaury Pouly <amaury.pouly@gmail.com> | 2013-06-16 15:58:36 +0200 |
commit | 0fa014a6fe7be43a827d4f4c7da63f1113e226c0 (patch) | |
tree | 474c9131300716597acaea044e37df974725318f /firmware | |
parent | 3d62000fcb3d191ca56bb135c360d1c8bedee0a2 (diff) | |
download | rockbox-0fa014a6fe7be43a827d4f4c7da63f1113e226c0.tar.gz rockbox-0fa014a6fe7be43a827d4f4c7da63f1113e226c0.zip |
imx233: rewrite i2c using new register headers
Change-Id: Ieffb389fb74404e86d8ba51ee8c48bab6b299763
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/target/arm/imx233/i2c-imx233.c | 31 | ||||
-rw-r--r-- | firmware/target/arm/imx233/i2c-imx233.h | 89 |
2 files changed, 18 insertions, 102 deletions
diff --git a/firmware/target/arm/imx233/i2c-imx233.c b/firmware/target/arm/imx233/i2c-imx233.c index 7846a0c2cd..f72be503fa 100644 --- a/firmware/target/arm/imx233/i2c-imx233.c +++ b/firmware/target/arm/imx233/i2c-imx233.c | |||
@@ -82,15 +82,14 @@ void INT_I2C_DMA(void) | |||
82 | 82 | ||
83 | void imx233_i2c_init(void) | 83 | void imx233_i2c_init(void) |
84 | { | 84 | { |
85 | //imx233_reset_block(&HW_I2C_CTRL0); | 85 | BF_SET(I2C_CTRL0, SFTRST); |
86 | __REG_SET(HW_I2C_CTRL0) = __BLOCK_SFTRST; | ||
87 | /* setup pins (must be done when shutdown) */ | 86 | /* setup pins (must be done when shutdown) */ |
88 | imx233_pinctrl_acquire_pin(0, 30, "i2c"); | 87 | imx233_pinctrl_acquire_pin(0, 30, "i2c"); |
89 | imx233_pinctrl_acquire_pin(0, 31, "i2c"); | 88 | imx233_pinctrl_acquire_pin(0, 31, "i2c"); |
90 | imx233_set_pin_function(0, 30, PINCTRL_FUNCTION_MAIN); | 89 | imx233_set_pin_function(0, 30, PINCTRL_FUNCTION_MAIN); |
91 | imx233_set_pin_function(0, 31, PINCTRL_FUNCTION_MAIN); | 90 | imx233_set_pin_function(0, 31, PINCTRL_FUNCTION_MAIN); |
92 | /* clear softreset */ | 91 | /* clear softreset */ |
93 | __REG_CLR(HW_I2C_CTRL0) = __BLOCK_SFTRST | __BLOCK_CLKGATE; | 92 | imx233_reset_block(&HW_I2C_CTRL0); |
94 | /* Errata: | 93 | /* Errata: |
95 | * When RETAIN_CLOCK is set, the ninth clock pulse (ACK) is not generated. However, the SDA | 94 | * When RETAIN_CLOCK is set, the ninth clock pulse (ACK) is not generated. However, the SDA |
96 | * line is read at the proper timing interval. If RETAIN_CLOCK is cleared, the ninth clock pulse is | 95 | * line is read at the proper timing interval. If RETAIN_CLOCK is cleared, the ninth clock pulse is |
@@ -98,8 +97,8 @@ void imx233_i2c_init(void) | |||
98 | * HW_I2C_CTRL1[ACK_MODE] has default value of 0. It should be set to 1 to enable the fix for | 97 | * HW_I2C_CTRL1[ACK_MODE] has default value of 0. It should be set to 1 to enable the fix for |
99 | * this issue. | 98 | * this issue. |
100 | */ | 99 | */ |
101 | __REG_SET(HW_I2C_CTRL1) = HW_I2C_CTRL1__ACK_MODE; | 100 | BF_SET(I2C_CTRL1, ACK_MODE); |
102 | __REG_SET(HW_I2C_CTRL0) = __BLOCK_CLKGATE; | 101 | BF_SET(I2C_CTRL0, CLKGATE); |
103 | /* Fast-mode @ 400K */ | 102 | /* Fast-mode @ 400K */ |
104 | HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */ | 103 | HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */ |
105 | HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */ | 104 | HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */ |
@@ -113,7 +112,7 @@ void imx233_i2c_begin(void) | |||
113 | { | 112 | { |
114 | mutex_lock(&i2c_mutex); | 113 | mutex_lock(&i2c_mutex); |
115 | /* wakeup */ | 114 | /* wakeup */ |
116 | __REG_CLR(HW_I2C_CTRL0) = __BLOCK_CLKGATE; | 115 | BF_CLR(I2C_CTRL0, CLKGATE); |
117 | i2c_nr_stages = 0; | 116 | i2c_nr_stages = 0; |
118 | i2c_buffer_end = 0; | 117 | i2c_buffer_end = 0; |
119 | } | 118 | } |
@@ -148,7 +147,7 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, | |||
148 | i2c_stage[i2c_nr_stages - 1].dma.next = &i2c_stage[i2c_nr_stages].dma; | 147 | i2c_stage[i2c_nr_stages - 1].dma.next = &i2c_stage[i2c_nr_stages].dma; |
149 | i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__CHAIN; | 148 | i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__CHAIN; |
150 | if(!start) | 149 | if(!start) |
151 | i2c_stage[i2c_nr_stages - 1].ctrl0 |= HW_I2C_CTRL0__RETAIN_CLOCK; | 150 | i2c_stage[i2c_nr_stages - 1].ctrl0 |= BM_I2C_CTRL0_RETAIN_CLOCK; |
152 | } | 151 | } |
153 | i2c_stage[i2c_nr_stages].dma.buffer = i2c_buffer + start_off; | 152 | i2c_stage[i2c_nr_stages].dma.buffer = i2c_buffer + start_off; |
154 | i2c_stage[i2c_nr_stages].dma.next = NULL; | 153 | i2c_stage[i2c_nr_stages].dma.next = NULL; |
@@ -158,11 +157,9 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer, | |||
158 | 1 << HW_APB_CHx_CMD__CMDWORDS_BP | | 157 | 1 << HW_APB_CHx_CMD__CMDWORDS_BP | |
159 | size << HW_APB_CHx_CMD__XFER_COUNT_BP; | 158 | size << HW_APB_CHx_CMD__XFER_COUNT_BP; |
160 | /* assume that any read is final (send nak on last) */ | 159 | /* assume that any read is final (send nak on last) */ |
161 | i2c_stage[i2c_nr_stages].ctrl0 = size | | 160 | i2c_stage[i2c_nr_stages].ctrl0 = BF_OR6(I2C_CTRL0, |
162 | (transmit ? HW_I2C_CTRL0__TRANSMIT : HW_I2C_CTRL0__SEND_NAK_ON_LAST) | | 161 | XFER_COUNT(size), DIRECTION(transmit), SEND_NAK_ON_LAST(!transmit), |
163 | (start ? HW_I2C_CTRL0__PRE_SEND_START : 0) | | 162 | PRE_SEND_START(start), POST_SEND_STOP(stop), MASTER_MODE(1)); |
164 | (stop ? HW_I2C_CTRL0__POST_SEND_STOP : 0) | | ||
165 | HW_I2C_CTRL0__MASTER_MODE; | ||
166 | i2c_nr_stages++; | 163 | i2c_nr_stages++; |
167 | return I2C_SUCCESS; | 164 | return I2C_SUCCESS; |
168 | } | 165 | } |
@@ -185,7 +182,7 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout) | |||
185 | return I2C_ERROR; | 182 | return I2C_ERROR; |
186 | i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__SEMAPHORE | HW_APB_CHx_CMD__IRQONCMPLT; | 183 | i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__SEMAPHORE | HW_APB_CHx_CMD__IRQONCMPLT; |
187 | 184 | ||
188 | __REG_CLR(HW_I2C_CTRL1) = HW_I2C_CTRL1__ALL_IRQ; | 185 | BF_CLR(I2C_CTRL1, ALL_IRQ); |
189 | imx233_dma_reset_channel(APB_I2C); | 186 | imx233_dma_reset_channel(APB_I2C); |
190 | imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true); | 187 | imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true); |
191 | imx233_dma_enable_channel_interrupt(APB_I2C, true); | 188 | imx233_dma_enable_channel_interrupt(APB_I2C, true); |
@@ -197,16 +194,16 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout) | |||
197 | imx233_dma_reset_channel(APB_I2C); | 194 | imx233_dma_reset_channel(APB_I2C); |
198 | ret = I2C_TIMEOUT; | 195 | ret = I2C_TIMEOUT; |
199 | } | 196 | } |
200 | else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__MASTER_LOSS_IRQ) | 197 | else if(BF_RD(I2C_CTRL1, MASTER_LOSS_IRQ)) |
201 | ret = I2C_MASTER_LOSS; | 198 | ret = I2C_MASTER_LOSS; |
202 | else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ) | 199 | else if(BF_RD(I2C_CTRL1, NO_SLAVE_ACK_IRQ)) |
203 | ret= I2C_NO_SLAVE_ACK; | 200 | ret= I2C_NO_SLAVE_ACK; |
204 | else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__EARLY_TERM_IRQ) | 201 | else if(BF_RD(I2C_CTRL1, EARLY_TERM_IRQ)) |
205 | ret = I2C_SLAVE_NAK; | 202 | ret = I2C_SLAVE_NAK; |
206 | else | 203 | else |
207 | ret = imx233_i2c_finalize(); | 204 | ret = imx233_i2c_finalize(); |
208 | /* sleep */ | 205 | /* sleep */ |
209 | __REG_SET(HW_I2C_CTRL0) = __BLOCK_CLKGATE; | 206 | BF_SET(I2C_CTRL0, CLKGATE); |
210 | mutex_unlock(&i2c_mutex); | 207 | mutex_unlock(&i2c_mutex); |
211 | return ret; | 208 | return ret; |
212 | } | 209 | } |
diff --git a/firmware/target/arm/imx233/i2c-imx233.h b/firmware/target/arm/imx233/i2c-imx233.h index 6d4ef236ff..174fe020ce 100644 --- a/firmware/target/arm/imx233/i2c-imx233.h +++ b/firmware/target/arm/imx233/i2c-imx233.h | |||
@@ -26,92 +26,11 @@ | |||
26 | #include "system-target.h" | 26 | #include "system-target.h" |
27 | #include "i2c.h" | 27 | #include "i2c.h" |
28 | 28 | ||
29 | #define HW_I2C_BASE 0x80058000 | 29 | #include "regs/regs-i2c.h" |
30 | 30 | ||
31 | #define HW_I2C_CTRL0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x0)) | 31 | #define BM_I2C_CTRL1_ALL_IRQ \ |
32 | #define HW_I2C_CTRL0__XFER_COUNT_BM 0xffff | 32 | BM_OR8(I2C_CTRL1, SLAVE_IRQ, SLAVE_STOP_IRQ, MASTER_LOSS_IRQ, EARLY_TERM_IRQ, \ |
33 | #define HW_I2C_CTRL0__TRANSMIT (1 << 16) | 33 | OVERSIZE_XFER_TERM_IRQ, NO_SLAVE_ACK_IRQ, DATA_ENGINE_CMPLT_IRQ, BUS_FREE_IRQ) |
34 | #define HW_I2C_CTRL0__MASTER_MODE (1 << 17) | ||
35 | #define HW_I2C_CTRL0__SLAVE_ADDRESS_ENABLE (1 << 18) | ||
36 | #define HW_I2C_CTRL0__PRE_SEND_START (1 << 19) | ||
37 | #define HW_I2C_CTRL0__POST_SEND_STOP (1 << 20) | ||
38 | #define HW_I2C_CTRL0__RETAIN_CLOCK (1 << 21) | ||
39 | #define HW_I2C_CTRL0__CLOCK_HELD (1 << 22) | ||
40 | #define HW_I2C_CTRL0__PIO_MODE (1 << 24) | ||
41 | #define HW_I2C_CTRL0__SEND_NAK_ON_LAST (1 << 25) | ||
42 | #define HW_I2C_CTRL0__ACKNOWLEDGE (1 << 26) | ||
43 | #define HW_I2C_CTRL0__RUN (1 << 29) | ||
44 | |||
45 | #define HW_I2C_TIMING0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x10)) | ||
46 | #define HW_I2C_TIMING0__RECV_COUNT_BM 0x3ff | ||
47 | #define HW_I2C_TIMING0__HIGH_COUNT_BM (0x3ff << 16) | ||
48 | #define HW_I2C_TIMING0__HIGH_COUNT_BP 16 | ||
49 | |||
50 | #define HW_I2C_TIMING1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x20)) | ||
51 | #define HW_I2C_TIMING1__XMIT_COUNT_BM 0x3ff | ||
52 | #define HW_I2C_TIMING1__LOW_COUNT_BM (0x3ff << 16) | ||
53 | #define HW_I2C_TIMING1__LOW_COUNT_BP 16 | ||
54 | |||
55 | #define HW_I2C_TIMING2 (*(volatile uint32_t *)(HW_I2C_BASE + 0x30)) | ||
56 | #define HW_I2C_TIMING2__LEADIN_COUNT_BM 0x3ff | ||
57 | #define HW_I2C_TIMING2__BUS_FREE_BM (0x3ff << 16) | ||
58 | #define HW_I2C_TIMING2__BUS_FREE_BP 16 | ||
59 | |||
60 | #define HW_I2C_CTRL1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x40)) | ||
61 | #define HW_I2C_CTRL1__SLAVE_IRQ (1 << 0) | ||
62 | #define HW_I2C_CTRL1__SLAVE_STOP_IRQ (1 << 1) | ||
63 | #define HW_I2C_CTRL1__MASTER_LOSS_IRQ (1 << 2) | ||
64 | #define HW_I2C_CTRL1__EARLY_TERM_IRQ (1 << 3) | ||
65 | #define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ (1 << 4) | ||
66 | #define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ (1 << 5) | ||
67 | #define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ (1 << 6) | ||
68 | #define HW_I2C_CTRL1__BUS_FREE_IRQ (1 << 7) | ||
69 | #define HW_I2C_CTRL1__SLAVE_IRQ_EN (1 << 8) | ||
70 | #define HW_I2C_CTRL1__SLAVE_STOP_IRQ_EN (1 << 9) | ||
71 | #define HW_I2C_CTRL1__MASTER_LOSS_IRQ_EN (1 << 10) | ||
72 | #define HW_I2C_CTRL1__EARLY_TERM_IRQ_EN (1 << 11) | ||
73 | #define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) | ||
74 | #define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ_EN (1 << 13) | ||
75 | #define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ_EN (1 << 14) | ||
76 | #define HW_I2C_CTRL1__BUS_FREE_IRQ_EN (1 << 15) | ||
77 | #define HW_I2C_CTRL1__BCAST_SLAVE_EN (1 << 24) | ||
78 | #define HW_I2C_CTRL1__FORCE_CLK_IDLE (1 << 25) | ||
79 | #define HW_I2C_CTRL1__FORCE_DATA_IDLE (1 << 26) | ||
80 | #define HW_I2C_CTRL1__ACK_MODE (1 << 27) | ||
81 | #define HW_I2C_CTRL1__CLR_GOT_A_NAK (1 << 28) | ||
82 | #define HW_I2C_CTRL1__ALL_IRQ 0xff | ||
83 | #define HW_I2C_CTRL1__ALL_IRQ_EN 0xff00 | ||
84 | |||
85 | #define HW_I2C_STAT (*(volatile uint32_t *)(HW_I2C_BASE + 0x50)) | ||
86 | #define HW_I2C_STAT__SLAVE_IRQ_SUMMARY (1 << 0) | ||
87 | #define HW_I2C_STAT__SLAVE_STOP_IRQ_SUMMARY (1 << 1) | ||
88 | #define HW_I2C_STAT__MASTER_LOSS_IRQ_SUMMARY (1 << 2) | ||
89 | #define HW_I2C_STAT__EARLY_TERM_IRQ_SUMMARY (1 << 3) | ||
90 | #define HW_I2C_STAT__OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) | ||
91 | #define HW_I2C_STAT__NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) | ||
92 | #define HW_I2C_STAT__DATA_ENGINE_COMPLT_IRQ_SUMMARY (1 << 6) | ||
93 | #define HW_I2C_STAT__BUS_FREE_IRQ_SUMMARY (1 << 7) | ||
94 | #define HW_I2C_STAT__SLAVE_BUSY (1 << 8) | ||
95 | #define HW_I2C_STAT__DATA_ENGINE_BUSY (1 << 9) | ||
96 | #define HW_I2C_STAT__CLK_GEN_BUSY (1 << 10) | ||
97 | #define HW_I2C_STAT__BUS_BUSY (1 << 11) | ||
98 | #define HW_I2C_STAT__DATA_ENGINE_DMA_WAIT (1 << 12) | ||
99 | #define HW_I2C_STAT__SLAVE_SEARCHING (1 << 13) | ||
100 | #define HW_I2C_STAT__SLAVE_FOUND (1 << 14) | ||
101 | #define HW_I2C_STAT__SLAVE_ADDR_EQ_ZERO (1 << 15) | ||
102 | #define HW_I2C_STAT__RCVD_SLAVE_ADDR_BM (0xff << 16) | ||
103 | #define HW_I2C_STAT__RCVD_SLAVE_ADDR_BP 16 | ||
104 | #define HW_I2C_STAT__GOT_A_NAK (1 << 28) | ||
105 | #define HW_I2C_STAT__ANY_ENABLED_IRQ (1 << 29) | ||
106 | #define HW_I2C_STAT__MASTER_PRESENT (1 << 31) | ||
107 | |||
108 | #define HW_I2C_DATA (*(volatile uint32_t *)(HW_I2C_BASE + 0x60)) | ||
109 | |||
110 | #define HW_I2C_DEBUG0 (*(volatile uint32_t *)(HW_I2C_BASE + 0x70)) | ||
111 | |||
112 | #define HW_I2C_DEBUG1 (*(volatile uint32_t *)(HW_I2C_BASE + 0x80)) | ||
113 | |||
114 | #define HW_I2C_VERSION (*(volatile uint32_t *)(HW_I2C_BASE + 0x90)) | ||
115 | 34 | ||
116 | enum imx233_i2c_error_t | 35 | enum imx233_i2c_error_t |
117 | { | 36 | { |