imx233: rewrite i2c using new register headers

Change-Id: Ieffb389fb74404e86d8ba51ee8c48bab6b299763

2 files changed, 18 insertions, 102 deletions

diff --git a/firmware/target/arm/imx233/i2c-imx233.c b/firmware/target/arm/imx233/i2c-imx233.c
index 7846a0c2cd..f72be503fa 100644
--- a/firmware/target/arm/imx233/i2c-imx233.c
+++ b/firmware/target/arm/imx233/i2c-imx233.c
@@ -82,15 +82,14 @@ void INT_I2C_DMA(void)
 
 void imx233_i2c_init(void)
 {
-    //imx233_reset_block(&HW_I2C_CTRL0);
-    __REG_SET(HW_I2C_CTRL0) = __BLOCK_SFTRST;
+    BF_SET(I2C_CTRL0, SFTRST);
     /* setup pins (must be done when shutdown) */
     imx233_pinctrl_acquire_pin(0, 30, "i2c");
     imx233_pinctrl_acquire_pin(0, 31, "i2c");
     imx233_set_pin_function(0, 30, PINCTRL_FUNCTION_MAIN);
     imx233_set_pin_function(0, 31, PINCTRL_FUNCTION_MAIN);
     /* clear softreset */
-    __REG_CLR(HW_I2C_CTRL0) = __BLOCK_SFTRST | __BLOCK_CLKGATE;
+    imx233_reset_block(&HW_I2C_CTRL0);
     /* Errata:
      * When RETAIN_CLOCK is set, the ninth clock pulse (ACK) is not generated. However, the SDA
      * line is read at the proper timing interval. If RETAIN_CLOCK is cleared, the ninth clock pulse is
@@ -98,8 +97,8 @@ void imx233_i2c_init(void)
      * HW_I2C_CTRL1[ACK_MODE] has default value of 0. It should be set to 1 to enable the fix for
      * this issue.
      */
-    __REG_SET(HW_I2C_CTRL1) = HW_I2C_CTRL1__ACK_MODE;
-    __REG_SET(HW_I2C_CTRL0) = __BLOCK_CLKGATE;
+    BF_SET(I2C_CTRL1, ACK_MODE);
+    BF_SET(I2C_CTRL0, CLKGATE);
     /* Fast-mode @ 400K */
     HW_I2C_TIMING0 = 0x000F0007; /* tHIGH=0.6us, read at 0.3us */
     HW_I2C_TIMING1 = 0x001F000F; /* tLOW=1.3us, write at 0.6us */
@@ -113,7 +112,7 @@ void imx233_i2c_begin(void)
 {
     mutex_lock(&i2c_mutex);
     /* wakeup */
-    __REG_CLR(HW_I2C_CTRL0) = __BLOCK_CLKGATE;
+    BF_CLR(I2C_CTRL0, CLKGATE);
     i2c_nr_stages = 0;
     i2c_buffer_end = 0;
 }
@@ -148,7 +147,7 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer,
         i2c_stage[i2c_nr_stages - 1].dma.next = &i2c_stage[i2c_nr_stages].dma;
         i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__CHAIN;
         if(!start)
-            i2c_stage[i2c_nr_stages - 1].ctrl0 |= HW_I2C_CTRL0__RETAIN_CLOCK;
+            i2c_stage[i2c_nr_stages - 1].ctrl0 |= BM_I2C_CTRL0_RETAIN_CLOCK;
     }
     i2c_stage[i2c_nr_stages].dma.buffer = i2c_buffer + start_off;
     i2c_stage[i2c_nr_stages].dma.next = NULL;
@@ -158,11 +157,9 @@ enum imx233_i2c_error_t imx233_i2c_add(bool start, bool transmit, void *buffer,
         1 << HW_APB_CHx_CMD__CMDWORDS_BP |
         size << HW_APB_CHx_CMD__XFER_COUNT_BP;
     /* assume that any read is final (send nak on last) */
-    i2c_stage[i2c_nr_stages].ctrl0 = size |
-        (transmit ? HW_I2C_CTRL0__TRANSMIT : HW_I2C_CTRL0__SEND_NAK_ON_LAST) |
-        (start ? HW_I2C_CTRL0__PRE_SEND_START : 0) |
-        (stop ? HW_I2C_CTRL0__POST_SEND_STOP : 0) |
-        HW_I2C_CTRL0__MASTER_MODE;
+    i2c_stage[i2c_nr_stages].ctrl0 = BF_OR6(I2C_CTRL0,
+        XFER_COUNT(size), DIRECTION(transmit), SEND_NAK_ON_LAST(!transmit),
+        PRE_SEND_START(start), POST_SEND_STOP(stop), MASTER_MODE(1));
     i2c_nr_stages++;
     return I2C_SUCCESS;
 }
@@ -185,7 +182,7 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
         return I2C_ERROR;
     i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__SEMAPHORE | HW_APB_CHx_CMD__IRQONCMPLT;
 
-    __REG_CLR(HW_I2C_CTRL1) = HW_I2C_CTRL1__ALL_IRQ;
+    BF_CLR(I2C_CTRL1, ALL_IRQ);
     imx233_dma_reset_channel(APB_I2C);
     imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true);
     imx233_dma_enable_channel_interrupt(APB_I2C, true);
@@ -197,16 +194,16 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
         imx233_dma_reset_channel(APB_I2C);
         ret = I2C_TIMEOUT;
     }
-    else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__MASTER_LOSS_IRQ)
+    else if(BF_RD(I2C_CTRL1, MASTER_LOSS_IRQ))
         ret = I2C_MASTER_LOSS;
-    else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ)
+    else if(BF_RD(I2C_CTRL1, NO_SLAVE_ACK_IRQ))
         ret= I2C_NO_SLAVE_ACK;
-    else if(HW_I2C_CTRL1 & HW_I2C_CTRL1__EARLY_TERM_IRQ)
+    else if(BF_RD(I2C_CTRL1, EARLY_TERM_IRQ))
         ret = I2C_SLAVE_NAK;
     else
         ret = imx233_i2c_finalize();
     /* sleep */
-    __REG_SET(HW_I2C_CTRL0) = __BLOCK_CLKGATE;
+    BF_SET(I2C_CTRL0, CLKGATE);
     mutex_unlock(&i2c_mutex);
     return ret;
 }
diff --git a/firmware/target/arm/imx233/i2c-imx233.h b/firmware/target/arm/imx233/i2c-imx233.h
index 6d4ef236ff..174fe020ce 100644
--- a/firmware/target/arm/imx233/i2c-imx233.h
+++ b/firmware/target/arm/imx233/i2c-imx233.h
@@ -26,92 +26,11 @@
 #include "system-target.h"
 #include "i2c.h"
 
-#define HW_I2C_BASE         0x80058000 
+#include "regs/regs-i2c.h"
 
-#define HW_I2C_CTRL0        (*(volatile uint32_t *)(HW_I2C_BASE + 0x0))
-#define HW_I2C_CTRL0__XFER_COUNT_BM     0xffff
-#define HW_I2C_CTRL0__TRANSMIT          (1 << 16)
-#define HW_I2C_CTRL0__MASTER_MODE       (1 << 17)
-#define HW_I2C_CTRL0__SLAVE_ADDRESS_ENABLE  (1 << 18)
-#define HW_I2C_CTRL0__PRE_SEND_START    (1 << 19)
-#define HW_I2C_CTRL0__POST_SEND_STOP    (1 << 20)
-#define HW_I2C_CTRL0__RETAIN_CLOCK      (1 << 21)
-#define HW_I2C_CTRL0__CLOCK_HELD        (1 << 22)
-#define HW_I2C_CTRL0__PIO_MODE          (1 << 24)
-#define HW_I2C_CTRL0__SEND_NAK_ON_LAST  (1 << 25)
-#define HW_I2C_CTRL0__ACKNOWLEDGE       (1 << 26)
-#define HW_I2C_CTRL0__RUN               (1 << 29)
-
-#define HW_I2C_TIMING0      (*(volatile uint32_t *)(HW_I2C_BASE + 0x10))
-#define HW_I2C_TIMING0__RECV_COUNT_BM   0x3ff
-#define HW_I2C_TIMING0__HIGH_COUNT_BM   (0x3ff << 16)
-#define HW_I2C_TIMING0__HIGH_COUNT_BP   16
-
-#define HW_I2C_TIMING1      (*(volatile uint32_t *)(HW_I2C_BASE + 0x20))
-#define HW_I2C_TIMING1__XMIT_COUNT_BM   0x3ff
-#define HW_I2C_TIMING1__LOW_COUNT_BM    (0x3ff << 16)
-#define HW_I2C_TIMING1__LOW_COUNT_BP    16
-
-#define HW_I2C_TIMING2      (*(volatile uint32_t *)(HW_I2C_BASE + 0x30))
-#define HW_I2C_TIMING2__LEADIN_COUNT_BM 0x3ff
-#define HW_I2C_TIMING2__BUS_FREE_BM     (0x3ff << 16)
-#define HW_I2C_TIMING2__BUS_FREE_BP     16
-
-#define HW_I2C_CTRL1        (*(volatile uint32_t *)(HW_I2C_BASE + 0x40))
-#define HW_I2C_CTRL1__SLAVE_IRQ         (1 << 0)
-#define HW_I2C_CTRL1__SLAVE_STOP_IRQ    (1 << 1)
-#define HW_I2C_CTRL1__MASTER_LOSS_IRQ   (1 << 2)
-#define HW_I2C_CTRL1__EARLY_TERM_IRQ    (1 << 3)
-#define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ    (1 << 4)
-#define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ  (1 << 5)
-#define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ    (1 << 6)
-#define HW_I2C_CTRL1__BUS_FREE_IRQ      (1 << 7)
-#define HW_I2C_CTRL1__SLAVE_IRQ_EN      (1 << 8)
-#define HW_I2C_CTRL1__SLAVE_STOP_IRQ_EN (1 << 9)
-#define HW_I2C_CTRL1__MASTER_LOSS_IRQ_EN    (1 << 10)
-#define HW_I2C_CTRL1__EARLY_TERM_IRQ_EN (1 << 11)
-#define HW_I2C_CTRL1__OVERSIZE_XFER_TERM_IRQ_EN (1 << 12)
-#define HW_I2C_CTRL1__NO_SLAVE_ACK_IRQ_EN   (1 << 13)
-#define HW_I2C_CTRL1__DATA_ENGINE_COMPLT_IRQ_EN (1 << 14)
-#define HW_I2C_CTRL1__BUS_FREE_IRQ_EN   (1 << 15)
-#define HW_I2C_CTRL1__BCAST_SLAVE_EN    (1 << 24)
-#define HW_I2C_CTRL1__FORCE_CLK_IDLE    (1 << 25)
-#define HW_I2C_CTRL1__FORCE_DATA_IDLE   (1 << 26)
-#define HW_I2C_CTRL1__ACK_MODE          (1 << 27)
-#define HW_I2C_CTRL1__CLR_GOT_A_NAK     (1 << 28)
-#define HW_I2C_CTRL1__ALL_IRQ           0xff
-#define HW_I2C_CTRL1__ALL_IRQ_EN        0xff00
-
-#define HW_I2C_STAT         (*(volatile uint32_t *)(HW_I2C_BASE + 0x50))
-#define HW_I2C_STAT__SLAVE_IRQ_SUMMARY          (1 << 0)
-#define HW_I2C_STAT__SLAVE_STOP_IRQ_SUMMARY     (1 << 1)
-#define HW_I2C_STAT__MASTER_LOSS_IRQ_SUMMARY    (1 << 2)
-#define HW_I2C_STAT__EARLY_TERM_IRQ_SUMMARY     (1 << 3)
-#define HW_I2C_STAT__OVERSIZE_XFER_TERM_IRQ_SUMMARY     (1 << 4)
-#define HW_I2C_STAT__NO_SLAVE_ACK_IRQ_SUMMARY   (1 << 5)
-#define HW_I2C_STAT__DATA_ENGINE_COMPLT_IRQ_SUMMARY     (1 << 6)
-#define HW_I2C_STAT__BUS_FREE_IRQ_SUMMARY       (1 << 7)
-#define HW_I2C_STAT__SLAVE_BUSY                 (1 << 8)
-#define HW_I2C_STAT__DATA_ENGINE_BUSY           (1 << 9)
-#define HW_I2C_STAT__CLK_GEN_BUSY               (1 << 10)
-#define HW_I2C_STAT__BUS_BUSY                   (1 << 11)
-#define HW_I2C_STAT__DATA_ENGINE_DMA_WAIT       (1 << 12)
-#define HW_I2C_STAT__SLAVE_SEARCHING            (1 << 13)
-#define HW_I2C_STAT__SLAVE_FOUND                (1 << 14)
-#define HW_I2C_STAT__SLAVE_ADDR_EQ_ZERO         (1 << 15)
-#define HW_I2C_STAT__RCVD_SLAVE_ADDR_BM         (0xff << 16)
-#define HW_I2C_STAT__RCVD_SLAVE_ADDR_BP         16
-#define HW_I2C_STAT__GOT_A_NAK                  (1 << 28)
-#define HW_I2C_STAT__ANY_ENABLED_IRQ            (1 << 29)
-#define HW_I2C_STAT__MASTER_PRESENT             (1 << 31)
-
-#define HW_I2C_DATA         (*(volatile uint32_t *)(HW_I2C_BASE + 0x60))
-
-#define HW_I2C_DEBUG0       (*(volatile uint32_t *)(HW_I2C_BASE + 0x70))
-
-#define HW_I2C_DEBUG1       (*(volatile uint32_t *)(HW_I2C_BASE + 0x80))
-
-#define HW_I2C_VERSION      (*(volatile uint32_t *)(HW_I2C_BASE + 0x90))
+#define BM_I2C_CTRL1_ALL_IRQ \
+    BM_OR8(I2C_CTRL1, SLAVE_IRQ, SLAVE_STOP_IRQ, MASTER_LOSS_IRQ, EARLY_TERM_IRQ, \
+        OVERSIZE_XFER_TERM_IRQ, NO_SLAVE_ACK_IRQ, DATA_ENGINE_CMPLT_IRQ, BUS_FREE_IRQ)
 
 enum imx233_i2c_error_t
 {