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author | Rafaël Carré <rafael.carre@gmail.com> | 2009-06-29 14:29:14 +0000 |
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committer | Rafaël Carré <rafael.carre@gmail.com> | 2009-06-29 14:29:14 +0000 |
commit | b3ed33d04aec20568b8bb9616349e6d7e4c71882 (patch) | |
tree | fbbfbe3d48cf8e61fc822d7f6fc14db8f46810d6 /firmware/timer.c | |
parent | c34ca87b64b71741327ec2ca7908080427babab0 (diff) | |
download | rockbox-b3ed33d04aec20568b8bb9616349e6d7e4c71882.tar.gz rockbox-b3ed33d04aec20568b8bb9616349e6d7e4c71882.zip |
Move SH7034 timer code in the target tree
Add an argument int_prio to TIMER_START() macro because SH7034 needs it
Leaves a target specific code in timer_register (could be given to target code through timer_set and __timer_set() )
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21556 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/timer.c')
-rw-r--r-- | firmware/timer.c | 61 |
1 files changed, 5 insertions, 56 deletions
diff --git a/firmware/timer.c b/firmware/timer.c index 34b410c017..044b871b3f 100644 --- a/firmware/timer.c +++ b/firmware/timer.c | |||
@@ -42,15 +42,7 @@ static long SHAREDBSS_ATTR cycles_new = 0; | |||
42 | #endif | 42 | #endif |
43 | 43 | ||
44 | /* interrupt handler */ | 44 | /* interrupt handler */ |
45 | #if CONFIG_CPU == SH7034 | 45 | #if defined(CPU_PP) |
46 | void IMIA4(void) __attribute__((interrupt_handler)); | ||
47 | void IMIA4(void) | ||
48 | { | ||
49 | if (pfn_timer != NULL) | ||
50 | pfn_timer(); | ||
51 | and_b(~0x01, &TSR4); /* clear the interrupt */ | ||
52 | } | ||
53 | #elif defined(CPU_PP) | ||
54 | void TIMER2(void) | 46 | void TIMER2(void) |
55 | { | 47 | { |
56 | TIMER2_VAL; /* ACK interrupt */ | 48 | TIMER2_VAL; /* ACK interrupt */ |
@@ -72,43 +64,7 @@ void TIMER2(void) | |||
72 | 64 | ||
73 | static bool timer_set(long cycles, bool start) | 65 | static bool timer_set(long cycles, bool start) |
74 | { | 66 | { |
75 | #if CONFIG_CPU == SH7034 | 67 | #if defined(CPU_PP) |
76 | int phi = 0; /* bits for the prescaler */ | ||
77 | int prescale = 1; | ||
78 | |||
79 | while (cycles > 0x10000) | ||
80 | { /* work out the smallest prescaler that makes it fit */ | ||
81 | phi++; | ||
82 | prescale <<= 1; | ||
83 | cycles >>= 1; | ||
84 | } | ||
85 | |||
86 | if (prescale > 8) | ||
87 | return false; | ||
88 | |||
89 | if (start) | ||
90 | { | ||
91 | if (pfn_unregister != NULL) | ||
92 | { | ||
93 | pfn_unregister(); | ||
94 | pfn_unregister = NULL; | ||
95 | } | ||
96 | |||
97 | and_b(~0x10, &TSTR); /* Stop the timer 4 */ | ||
98 | and_b(~0x10, &TSNC); /* No synchronization */ | ||
99 | and_b(~0x10, &TMDR); /* Operate normally */ | ||
100 | |||
101 | TIER4 = 0xF9; /* Enable GRA match interrupt */ | ||
102 | } | ||
103 | |||
104 | TCR4 = 0x20 | phi; /* clear at GRA match, set prescaler */ | ||
105 | GRA4 = (unsigned short)(cycles - 1); | ||
106 | if (start || (TCNT4 >= GRA4)) | ||
107 | TCNT4 = 0; | ||
108 | and_b(~0x01, &TSR4); /* clear an eventual interrupt */ | ||
109 | |||
110 | return true; | ||
111 | #elif defined(CPU_PP) | ||
112 | if (cycles > 0x20000000 || cycles < 2) | 68 | if (cycles > 0x20000000 || cycles < 2) |
113 | return false; | 69 | return false; |
114 | 70 | ||
@@ -153,11 +109,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
153 | pfn_unregister = unregister_callback; | 109 | pfn_unregister = unregister_callback; |
154 | timer_prio = reg_prio; | 110 | timer_prio = reg_prio; |
155 | 111 | ||
156 | #if CONFIG_CPU == SH7034 | 112 | #if defined(CPU_PP) |
157 | IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */ | ||
158 | or_b(0x10, &TSTR); /* start timer 4 */ | ||
159 | return true; | ||
160 | #elif defined(CPU_PP) | ||
161 | /* unmask interrupt source */ | 113 | /* unmask interrupt source */ |
162 | #if NUM_CORES > 1 | 114 | #if NUM_CORES > 1 |
163 | if (core == COP) | 115 | if (core == COP) |
@@ -167,7 +119,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
167 | CPU_INT_EN = TIMER2_MASK; | 119 | CPU_INT_EN = TIMER2_MASK; |
168 | return true; | 120 | return true; |
169 | #else | 121 | #else |
170 | return __TIMER_START(); | 122 | return __TIMER_START(int_prio); |
171 | #endif | 123 | #endif |
172 | /* Cover for targets that don't use all these */ | 124 | /* Cover for targets that don't use all these */ |
173 | (void)reg_prio; | 125 | (void)reg_prio; |
@@ -185,10 +137,7 @@ bool timer_set_period(long cycles) | |||
185 | 137 | ||
186 | void timer_unregister(void) | 138 | void timer_unregister(void) |
187 | { | 139 | { |
188 | #if CONFIG_CPU == SH7034 | 140 | #if defined(CPU_PP) |
189 | and_b(~0x10, &TSTR); /* stop the timer 4 */ | ||
190 | IPRD = (IPRD & 0xFF0F); /* disable interrupt */ | ||
191 | #elif defined(CPU_PP) | ||
192 | TIMER2_CFG = 0; /* stop timer 2 */ | 141 | TIMER2_CFG = 0; /* stop timer 2 */ |
193 | CPU_INT_DIS = TIMER2_MASK; | 142 | CPU_INT_DIS = TIMER2_MASK; |
194 | COP_INT_DIS = TIMER2_MASK; | 143 | COP_INT_DIS = TIMER2_MASK; |