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authorRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:29:14 +0000
committerRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:29:14 +0000
commitb3ed33d04aec20568b8bb9616349e6d7e4c71882 (patch)
treefbbfbe3d48cf8e61fc822d7f6fc14db8f46810d6
parentc34ca87b64b71741327ec2ca7908080427babab0 (diff)
downloadrockbox-b3ed33d04aec20568b8bb9616349e6d7e4c71882.tar.gz
rockbox-b3ed33d04aec20568b8bb9616349e6d7e4c71882.zip
Move SH7034 timer code in the target tree
Add an argument int_prio to TIMER_START() macro because SH7034 needs it Leaves a target specific code in timer_register (could be given to target code through timer_set and __timer_set() ) git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21556 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/SOURCES3
-rw-r--r--firmware/export/timer.h6
-rw-r--r--firmware/target/arm/as3525/timer-target.h2
-rw-r--r--firmware/target/arm/at91sam/lyre_proto1/timer-target.h2
-rw-r--r--firmware/target/arm/imx31/gigabeat-s/timer-target.h2
-rw-r--r--firmware/target/arm/pnx0101/timer-target.h2
-rw-r--r--firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h2
-rw-r--r--firmware/target/arm/tcc780x/timer-target.h2
-rw-r--r--firmware/target/arm/tms320dm320/timer-target.h2
-rw-r--r--firmware/target/coldfire/timer-target.h2
-rw-r--r--firmware/target/mips/ingenic_jz47xx/timer-target.h2
-rw-r--r--firmware/target/sh/archos/timer-archos.c85
-rw-r--r--firmware/target/sh/archos/timer-target.h41
-rw-r--r--firmware/timer.c61
14 files changed, 147 insertions, 67 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index b2fbfa13f2..239eb92a92 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -461,6 +461,7 @@ drivers/i2c.c
461#ifdef ARCHOS_PLAYER 461#ifdef ARCHOS_PLAYER
462#ifndef SIMULATOR 462#ifndef SIMULATOR
463target/sh/archos/ata-archos.c 463target/sh/archos/ata-archos.c
464target/sh/archos/timer-archos.c
464target/sh/archos/ata-as-archos.S 465target/sh/archos/ata-as-archos.S
465target/sh/archos/player/button-player.c 466target/sh/archos/player/button-player.c
466target/sh/archos/player/hwcompat-player.c 467target/sh/archos/player/hwcompat-player.c
@@ -475,6 +476,7 @@ target/sh/archos/player/usb-player.c
475#ifdef ARCHOS_RECORDER 476#ifdef ARCHOS_RECORDER
476#ifndef SIMULATOR 477#ifndef SIMULATOR
477target/sh/archos/ata-archos.c 478target/sh/archos/ata-archos.c
479target/sh/archos/timer-archos.c
478target/sh/archos/ata-as-archos.S 480target/sh/archos/ata-as-archos.S
479target/sh/archos/lcd-archos-bitmap.c 481target/sh/archos/lcd-archos-bitmap.c
480target/sh/archos/lcd-as-archos-bitmap.S 482target/sh/archos/lcd-as-archos-bitmap.S
@@ -488,6 +490,7 @@ target/sh/archos/recorder/usb-recorder.c
488#if defined(ARCHOS_FMRECORDER) || defined(ARCHOS_RECORDERV2) 490#if defined(ARCHOS_FMRECORDER) || defined(ARCHOS_RECORDERV2)
489#ifndef SIMULATOR 491#ifndef SIMULATOR
490target/sh/archos/ata-archos.c 492target/sh/archos/ata-archos.c
493target/sh/archos/timer-archos.c
491target/sh/archos/ata-as-archos.S 494target/sh/archos/ata-as-archos.S
492target/sh/archos/lcd-archos-bitmap.c 495target/sh/archos/lcd-archos-bitmap.c
493target/sh/archos/lcd-as-archos-bitmap.S 496target/sh/archos/lcd-as-archos-bitmap.S
diff --git a/firmware/export/timer.h b/firmware/export/timer.h
index b758f57ae5..f3faf0908e 100644
--- a/firmware/export/timer.h
+++ b/firmware/export/timer.h
@@ -31,11 +31,13 @@
31#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 || CONFIG_CPU == TCC7801 \ 31#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320 || CONFIG_CPU == TCC7801 \
32 || defined(CPU_TCC77X) || CONFIG_CPU == AS3525 || CONFIG_CPU == IMX31L \ 32 || defined(CPU_TCC77X) || CONFIG_CPU == AS3525 || CONFIG_CPU == IMX31L \
33 || CONFIG_CPU == JZ4732 || CONFIG_CPU == PNX0101 \ 33 || CONFIG_CPU == JZ4732 || CONFIG_CPU == PNX0101 \
34 || defined(CPU_COLDFIRE) 34 || defined(CPU_COLDFIRE) || CONFIG_CPU == SH7034
35 #include "timer-target.h" 35 #include "timer-target.h"
36#elif defined(SIMULATOR) 36#elif defined(SIMULATOR)
37 #define TIMER_FREQ 1000000 37 #define TIMER_FREQ 1000000
38#else 38#endif
39
40#ifndef TIMER_FREQ
39 #define TIMER_FREQ CPU_FREQ 41 #define TIMER_FREQ CPU_FREQ
40#endif 42#endif
41bool timer_register(int reg_prio, void (*unregister_callback)(void), 43bool timer_register(int reg_prio, void (*unregister_callback)(void),
diff --git a/firmware/target/arm/as3525/timer-target.h b/firmware/target/arm/as3525/timer-target.h
index b1bdfed78f..d42afaa2c4 100644
--- a/firmware/target/arm/as3525/timer-target.h
+++ b/firmware/target/arm/as3525/timer-target.h
@@ -30,7 +30,7 @@ void __timer_stop(void);
30#define __TIMER_SET(cycles, set) \ 30#define __TIMER_SET(cycles, set) \
31 __timer_set(cycles, set) 31 __timer_set(cycles, set)
32 32
33#define __TIMER_START() \ 33#define __TIMER_START(int_prio) \
34 __timer_start() 34 __timer_start()
35 35
36#define __TIMER_STOP(...) \ 36#define __TIMER_STOP(...) \
diff --git a/firmware/target/arm/at91sam/lyre_proto1/timer-target.h b/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
index b8298d3d77..1db63c5211 100644
--- a/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
+++ b/firmware/target/arm/at91sam/lyre_proto1/timer-target.h
@@ -32,7 +32,7 @@ void __timer_stop(void);
32#define __TIMER_SET(cycles, set) \ 32#define __TIMER_SET(cycles, set) \
33 __timer_set(cycles, set) 33 __timer_set(cycles, set)
34 34
35#define __TIMER_START() \ 35#define __TIMER_START(int_prio) \
36 __timer_start() 36 __timer_start()
37 37
38#define __TIMER_STOP(...) \ 38#define __TIMER_STOP(...) \
diff --git a/firmware/target/arm/imx31/gigabeat-s/timer-target.h b/firmware/target/arm/imx31/gigabeat-s/timer-target.h
index f019a45519..4ea459719c 100644
--- a/firmware/target/arm/imx31/gigabeat-s/timer-target.h
+++ b/firmware/target/arm/imx31/gigabeat-s/timer-target.h
@@ -31,7 +31,7 @@ void _timer_stop(void);
31#define __TIMER_SET(cycles, set) \ 31#define __TIMER_SET(cycles, set) \
32 _timer_set(cycles, set) 32 _timer_set(cycles, set)
33 33
34#define __TIMER_START() \ 34#define __TIMER_START(int_prio) \
35 _timer_start() 35 _timer_start()
36 36
37#define __TIMER_STOP(...) \ 37#define __TIMER_STOP(...) \
diff --git a/firmware/target/arm/pnx0101/timer-target.h b/firmware/target/arm/pnx0101/timer-target.h
index 853da07838..68d0e6b58a 100644
--- a/firmware/target/arm/pnx0101/timer-target.h
+++ b/firmware/target/arm/pnx0101/timer-target.h
@@ -30,7 +30,7 @@ void __timer_stop(void);
30#define __TIMER_SET(cycles, set) \ 30#define __TIMER_SET(cycles, set) \
31 __timer_set(cycles, set) 31 __timer_set(cycles, set)
32 32
33#define __TIMER_START() \ 33#define __TIMER_START(int_prio) \
34 __timer_start() 34 __timer_start()
35 35
36#define __TIMER_STOP(...) \ 36#define __TIMER_STOP(...) \
diff --git a/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h b/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
index 700833486d..577d0f947c 100644
--- a/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
+++ b/firmware/target/arm/s3c2440/gigabeat-fx/timer-target.h
@@ -32,7 +32,7 @@ void __timer_stop(void);
32#define __TIMER_SET(cycles, set) \ 32#define __TIMER_SET(cycles, set) \
33 __timer_set(cycles, set) 33 __timer_set(cycles, set)
34 34
35#define __TIMER_START() \ 35#define __TIMER_START(int_prio) \
36 __timer_start() 36 __timer_start()
37 37
38#define __TIMER_STOP(...) \ 38#define __TIMER_STOP(...) \
diff --git a/firmware/target/arm/tcc780x/timer-target.h b/firmware/target/arm/tcc780x/timer-target.h
index d6a8c4b0aa..c477ca6c70 100644
--- a/firmware/target/arm/tcc780x/timer-target.h
+++ b/firmware/target/arm/tcc780x/timer-target.h
@@ -31,7 +31,7 @@ void __timer_stop(void);
31#define __TIMER_SET(cycles, set) \ 31#define __TIMER_SET(cycles, set) \
32 __timer_set(cycles, set) 32 __timer_set(cycles, set)
33 33
34#define __TIMER_START() \ 34#define __TIMER_START(int_prio) \
35 __timer_start() 35 __timer_start()
36 36
37#define __TIMER_STOP(...) \ 37#define __TIMER_STOP(...) \
diff --git a/firmware/target/arm/tms320dm320/timer-target.h b/firmware/target/arm/tms320dm320/timer-target.h
index 9f3ffdf712..072f7e06a9 100644
--- a/firmware/target/arm/tms320dm320/timer-target.h
+++ b/firmware/target/arm/tms320dm320/timer-target.h
@@ -31,7 +31,7 @@ void __timer_stop(void);
31#define __TIMER_SET(cycles, set) \ 31#define __TIMER_SET(cycles, set) \
32 __timer_set(cycles, set) 32 __timer_set(cycles, set)
33 33
34#define __TIMER_START() \ 34#define __TIMER_START(int_prio) \
35 __timer_start() 35 __timer_start()
36 36
37#define __TIMER_STOP(...) \ 37#define __TIMER_STOP(...) \
diff --git a/firmware/target/coldfire/timer-target.h b/firmware/target/coldfire/timer-target.h
index 29488887e8..c7f695a0c8 100644
--- a/firmware/target/coldfire/timer-target.h
+++ b/firmware/target/coldfire/timer-target.h
@@ -31,7 +31,7 @@ void __timer_stop(void);
31#define __TIMER_SET(cycles, set) \ 31#define __TIMER_SET(cycles, set) \
32 __timer_set(cycles, set) 32 __timer_set(cycles, set)
33 33
34#define __TIMER_START() \ 34#define __TIMER_START(int_prio) \
35 __timer_start() 35 __timer_start()
36 36
37#define __TIMER_STOP(...) \ 37#define __TIMER_STOP(...) \
diff --git a/firmware/target/mips/ingenic_jz47xx/timer-target.h b/firmware/target/mips/ingenic_jz47xx/timer-target.h
index 2e072440ab..d42bd41bdc 100644
--- a/firmware/target/mips/ingenic_jz47xx/timer-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/timer-target.h
@@ -33,7 +33,7 @@ void __timer_stop(void);
33#define __TIMER_SET(cycles, set) \ 33#define __TIMER_SET(cycles, set) \
34 __timer_set(cycles, set) 34 __timer_set(cycles, set)
35 35
36#define __TIMER_START() \ 36#define __TIMER_START(int_prio) \
37 __timer_start() 37 __timer_start()
38 38
39#define __TIMER_STOP(...) \ 39#define __TIMER_STOP(...) \
diff --git a/firmware/target/sh/archos/timer-archos.c b/firmware/target/sh/archos/timer-archos.c
new file mode 100644
index 0000000000..e7526a8409
--- /dev/null
+++ b/firmware/target/sh/archos/timer-archos.c
@@ -0,0 +1,85 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2005 Jens Arnold
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21
22#include "cpu.h"
23#include "system.h"
24#include "timer.h"
25#include "timer-target.h"
26
27void IMIA4(void) __attribute__((interrupt_handler));
28void IMIA4(void)
29{
30 if (pfn_timer != NULL)
31 pfn_timer();
32 and_b(~0x01, &TSR4); /* clear the interrupt */
33}
34
35bool __timer_set(long cycles, bool start)
36{
37 int phi = 0; /* bits for the prescaler */
38 int prescale = 1;
39
40 while (cycles > 0x10000)
41 { /* work out the smallest prescaler that makes it fit */
42 phi++;
43 prescale <<= 1;
44 cycles >>= 1;
45 }
46
47 if (prescale > 8)
48 return false;
49
50 if (start)
51 {
52 if (pfn_unregister != NULL)
53 {
54 pfn_unregister();
55 pfn_unregister = NULL;
56 }
57
58 and_b(~0x10, &TSTR); /* Stop the timer 4 */
59 and_b(~0x10, &TSNC); /* No synchronization */
60 and_b(~0x10, &TMDR); /* Operate normally */
61
62 TIER4 = 0xF9; /* Enable GRA match interrupt */
63 }
64
65 TCR4 = 0x20 | phi; /* clear at GRA match, set prescaler */
66 GRA4 = (unsigned short)(cycles - 1);
67 if (start || (TCNT4 >= GRA4))
68 TCNT4 = 0;
69 and_b(~0x01, &TSR4); /* clear an eventual interrupt */
70
71 return true;
72}
73
74bool __timer_start(int int_prio)
75{
76 IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */
77 or_b(0x10, &TSTR); /* start timer 4 */
78 return true;
79}
80
81void __timer_stop(void)
82{
83 and_b(~0x10, &TSTR); /* stop the timer 4 */
84 IPRD = (IPRD & 0xFF0F); /* disable interrupt */
85}
diff --git a/firmware/target/sh/archos/timer-target.h b/firmware/target/sh/archos/timer-target.h
new file mode 100644
index 0000000000..08fcae1156
--- /dev/null
+++ b/firmware/target/sh/archos/timer-target.h
@@ -0,0 +1,41 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2005 Jens Arnold
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21#ifndef TIMER_TARGET_H
22#define TIMER_TARGET_H
23
24#include "config.h"
25
26bool __timer_set(long cycles, bool start);
27bool __timer_start(int int_prio);
28void __timer_stop(void);
29
30#define TIMER_FREQ CPU_FREQ
31
32#define __TIMER_SET(cycles, set) \
33 __timer_set(cycles, set)
34
35#define __TIMER_START(int_prio) \
36 __timer_start(int_prio)
37
38#define __TIMER_STOP(...) \
39 __timer_stop()
40
41#endif /* TIMER_TARGET_H */
diff --git a/firmware/timer.c b/firmware/timer.c
index 34b410c017..044b871b3f 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -42,15 +42,7 @@ static long SHAREDBSS_ATTR cycles_new = 0;
42#endif 42#endif
43 43
44/* interrupt handler */ 44/* interrupt handler */
45#if CONFIG_CPU == SH7034 45#if defined(CPU_PP)
46void IMIA4(void) __attribute__((interrupt_handler));
47void IMIA4(void)
48{
49 if (pfn_timer != NULL)
50 pfn_timer();
51 and_b(~0x01, &TSR4); /* clear the interrupt */
52}
53#elif defined(CPU_PP)
54void TIMER2(void) 46void TIMER2(void)
55{ 47{
56 TIMER2_VAL; /* ACK interrupt */ 48 TIMER2_VAL; /* ACK interrupt */
@@ -72,43 +64,7 @@ void TIMER2(void)
72 64
73static bool timer_set(long cycles, bool start) 65static bool timer_set(long cycles, bool start)
74{ 66{
75#if CONFIG_CPU == SH7034 67#if defined(CPU_PP)
76 int phi = 0; /* bits for the prescaler */
77 int prescale = 1;
78
79 while (cycles > 0x10000)
80 { /* work out the smallest prescaler that makes it fit */
81 phi++;
82 prescale <<= 1;
83 cycles >>= 1;
84 }
85
86 if (prescale > 8)
87 return false;
88
89 if (start)
90 {
91 if (pfn_unregister != NULL)
92 {
93 pfn_unregister();
94 pfn_unregister = NULL;
95 }
96
97 and_b(~0x10, &TSTR); /* Stop the timer 4 */
98 and_b(~0x10, &TSNC); /* No synchronization */
99 and_b(~0x10, &TMDR); /* Operate normally */
100
101 TIER4 = 0xF9; /* Enable GRA match interrupt */
102 }
103
104 TCR4 = 0x20 | phi; /* clear at GRA match, set prescaler */
105 GRA4 = (unsigned short)(cycles - 1);
106 if (start || (TCNT4 >= GRA4))
107 TCNT4 = 0;
108 and_b(~0x01, &TSR4); /* clear an eventual interrupt */
109
110 return true;
111#elif defined(CPU_PP)
112 if (cycles > 0x20000000 || cycles < 2) 68 if (cycles > 0x20000000 || cycles < 2)
113 return false; 69 return false;
114 70
@@ -153,11 +109,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
153 pfn_unregister = unregister_callback; 109 pfn_unregister = unregister_callback;
154 timer_prio = reg_prio; 110 timer_prio = reg_prio;
155 111
156#if CONFIG_CPU == SH7034 112#if defined(CPU_PP)
157 IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */
158 or_b(0x10, &TSTR); /* start timer 4 */
159 return true;
160#elif defined(CPU_PP)
161 /* unmask interrupt source */ 113 /* unmask interrupt source */
162#if NUM_CORES > 1 114#if NUM_CORES > 1
163 if (core == COP) 115 if (core == COP)
@@ -167,7 +119,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
167 CPU_INT_EN = TIMER2_MASK; 119 CPU_INT_EN = TIMER2_MASK;
168 return true; 120 return true;
169#else 121#else
170 return __TIMER_START(); 122 return __TIMER_START(int_prio);
171#endif 123#endif
172 /* Cover for targets that don't use all these */ 124 /* Cover for targets that don't use all these */
173 (void)reg_prio; 125 (void)reg_prio;
@@ -185,10 +137,7 @@ bool timer_set_period(long cycles)
185 137
186void timer_unregister(void) 138void timer_unregister(void)
187{ 139{
188#if CONFIG_CPU == SH7034 140#if defined(CPU_PP)
189 and_b(~0x10, &TSTR); /* stop the timer 4 */
190 IPRD = (IPRD & 0xFF0F); /* disable interrupt */
191#elif defined(CPU_PP)
192 TIMER2_CFG = 0; /* stop timer 2 */ 141 TIMER2_CFG = 0; /* stop timer 2 */
193 CPU_INT_DIS = TIMER2_MASK; 142 CPU_INT_DIS = TIMER2_MASK;
194 COP_INT_DIS = TIMER2_MASK; 143 COP_INT_DIS = TIMER2_MASK;