diff options
author | Rafaël Carré <rafael.carre@gmail.com> | 2009-06-29 14:28:49 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2009-06-29 14:28:49 +0000 |
commit | 15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6 (patch) | |
tree | 11fe9e6aada97782e66f0f3169cf39f43e0a2be0 /firmware/timer.c | |
parent | 2c10af5d3015be95020a8619c7ee657994f14558 (diff) | |
download | rockbox-15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6.tar.gz rockbox-15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6.zip |
Move Sansa AMS timer code in the target tree
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21552 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/timer.c')
-rw-r--r-- | firmware/timer.c | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/firmware/timer.c b/firmware/timer.c index 1cd913bb35..bcaacba307 100644 --- a/firmware/timer.c +++ b/firmware/timer.c | |||
@@ -61,14 +61,6 @@ void TIMER1(void) | |||
61 | pfn_timer(); | 61 | pfn_timer(); |
62 | TER1 = 0xff; /* clear all events */ | 62 | TER1 = 0xff; /* clear all events */ |
63 | } | 63 | } |
64 | #elif CONFIG_CPU == AS3525 | ||
65 | void INT_TIMER1(void) | ||
66 | { | ||
67 | if (pfn_timer != NULL) | ||
68 | pfn_timer(); | ||
69 | |||
70 | TIMER1_INTCLR = 0; /* clear interrupt */ | ||
71 | } | ||
72 | #elif defined(CPU_PP) | 64 | #elif defined(CPU_PP) |
73 | void TIMER2(void) | 65 | void TIMER2(void) |
74 | { | 66 | { |
@@ -171,25 +163,6 @@ static bool timer_set(long cycles, bool start) | |||
171 | and_b(~0x01, &TSR4); /* clear an eventual interrupt */ | 163 | and_b(~0x01, &TSR4); /* clear an eventual interrupt */ |
172 | 164 | ||
173 | return true; | 165 | return true; |
174 | #elif CONFIG_CPU == AS3525 | ||
175 | if (start) | ||
176 | { | ||
177 | if (pfn_unregister != NULL) | ||
178 | { | ||
179 | pfn_unregister(); | ||
180 | pfn_unregister = NULL; | ||
181 | } | ||
182 | } | ||
183 | |||
184 | TIMER1_LOAD = TIMER1_BGLOAD = cycles; | ||
185 | /* /!\ bit 4 (reserved) must not be modified | ||
186 | * periodic mode, interrupt enabled, no prescale, 32 bits counter */ | ||
187 | TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) | | ||
188 | TIMER_ENABLE | | ||
189 | TIMER_PERIODIC | | ||
190 | TIMER_INT_ENABLE | | ||
191 | TIMER_32_BIT; | ||
192 | return true; | ||
193 | #elif defined CPU_COLDFIRE | 166 | #elif defined CPU_COLDFIRE |
194 | if (prescale > 4096/CPUFREQ_MAX_MULT) | 167 | if (prescale > 4096/CPUFREQ_MAX_MULT) |
195 | return false; | 168 | return false; |
@@ -314,10 +287,6 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void), | |||
314 | irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); | 287 | irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); |
315 | irq_enable_int(IRQ_TIMER1); | 288 | irq_enable_int(IRQ_TIMER1); |
316 | return true; | 289 | return true; |
317 | #elif CONFIG_CPU == AS3525 | ||
318 | CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */ | ||
319 | VIC_INT_ENABLE |= INTERRUPT_TIMER1; | ||
320 | return true; | ||
321 | #else | 290 | #else |
322 | return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, | 291 | return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, |
323 | int_prio, timer_callback); | 292 | int_prio, timer_callback); |
@@ -351,10 +320,6 @@ void timer_unregister(void) | |||
351 | #elif CONFIG_CPU == PNX0101 | 320 | #elif CONFIG_CPU == PNX0101 |
352 | TIMER1.ctrl &= ~0x80; /* disable timer 1 */ | 321 | TIMER1.ctrl &= ~0x80; /* disable timer 1 */ |
353 | irq_disable_int(IRQ_TIMER1); | 322 | irq_disable_int(IRQ_TIMER1); |
354 | #elif CONFIG_CPU == AS3525 | ||
355 | TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */ | ||
356 | VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */ | ||
357 | CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */ | ||
358 | #else | 323 | #else |
359 | __TIMER_UNREGISTER(); | 324 | __TIMER_UNREGISTER(); |
360 | #endif | 325 | #endif |