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authorRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:28:49 +0000
committerRafaël Carré <rafael.carre@gmail.com>2009-06-29 14:28:49 +0000
commit15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6 (patch)
tree11fe9e6aada97782e66f0f3169cf39f43e0a2be0
parent2c10af5d3015be95020a8619c7ee657994f14558 (diff)
downloadrockbox-15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6.tar.gz
rockbox-15e40dd3a6ac8e9df88b77c0dbd9a90870ad91e6.zip
Move Sansa AMS timer code in the target tree
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21552 a1c6a512-1295-4272-9138-f99709370657
-rw-r--r--firmware/SOURCES1
-rw-r--r--firmware/target/arm/as3525/timer-as3525.c68
-rw-r--r--firmware/timer.c35
3 files changed, 69 insertions, 35 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES
index f6bc547f45..11f09e7062 100644
--- a/firmware/SOURCES
+++ b/firmware/SOURCES
@@ -372,6 +372,7 @@ target/arm/pnx0101/system-pnx0101.c
372#if CONFIG_CPU == AS3525 372#if CONFIG_CPU == AS3525
373target/arm/as3525/system-as3525.c 373target/arm/as3525/system-as3525.c
374target/arm/as3525/kernel-as3525.c 374target/arm/as3525/kernel-as3525.c
375target/arm/as3525/timer-as3525.c
375target/arm/as3525/ata_sd_as3525.c 376target/arm/as3525/ata_sd_as3525.c
376target/arm/as3525/power-as3525.c 377target/arm/as3525/power-as3525.c
377target/arm/as3525/usb-as3525.c 378target/arm/as3525/usb-as3525.c
diff --git a/firmware/target/arm/as3525/timer-as3525.c b/firmware/target/arm/as3525/timer-as3525.c
new file mode 100644
index 0000000000..755438a1f8
--- /dev/null
+++ b/firmware/target/arm/as3525/timer-as3525.c
@@ -0,0 +1,68 @@
1/***************************************************************************
2* __________ __ ___.
3* Open \______ \ ____ ____ | | _\_ |__ _______ ___
4* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7* \/ \/ \/ \/ \/
8* $Id$
9*
10* Copyright (C) 2008 Rafaël Carré
11*
12* This program is free software; you can redistribute it and/or
13* modify it under the terms of the GNU General Public License
14* as published by the Free Software Foundation; either version 2
15* of the License, or (at your option) any later version.
16*
17* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18* KIND, either express or implied.
19*
20****************************************************************************/
21
22#include "as3525.h"
23#include "timer.h"
24#include "stdlib.h"
25
26void INT_TIMER1(void)
27{
28 if (pfn_timer != NULL)
29 pfn_timer();
30
31 TIMER1_INTCLR = 0; /* clear interrupt */
32}
33
34bool __timer_set(long cycles, bool start)
35{
36 if (start)
37 {
38 if (pfn_unregister != NULL)
39 {
40 pfn_unregister();
41 pfn_unregister = NULL;
42 }
43 }
44
45 TIMER1_LOAD = TIMER1_BGLOAD = cycles;
46 /* /!\ bit 4 (reserved) must not be modified
47 * periodic mode, interrupt enabled, no prescale, 32 bits counter */
48 TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) |
49 TIMER_ENABLE |
50 TIMER_PERIODIC |
51 TIMER_INT_ENABLE |
52 TIMER_32_BIT;
53 return true;
54}
55
56bool __timer_register(void)
57{
58 CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */
59 VIC_INT_ENABLE |= INTERRUPT_TIMER1;
60 return true;
61}
62
63void __timer_unregister(void)
64{
65 TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */
66 VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */
67 CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */
68}
diff --git a/firmware/timer.c b/firmware/timer.c
index 1cd913bb35..bcaacba307 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -61,14 +61,6 @@ void TIMER1(void)
61 pfn_timer(); 61 pfn_timer();
62 TER1 = 0xff; /* clear all events */ 62 TER1 = 0xff; /* clear all events */
63} 63}
64#elif CONFIG_CPU == AS3525
65void INT_TIMER1(void)
66{
67 if (pfn_timer != NULL)
68 pfn_timer();
69
70 TIMER1_INTCLR = 0; /* clear interrupt */
71}
72#elif defined(CPU_PP) 64#elif defined(CPU_PP)
73void TIMER2(void) 65void TIMER2(void)
74{ 66{
@@ -171,25 +163,6 @@ static bool timer_set(long cycles, bool start)
171 and_b(~0x01, &TSR4); /* clear an eventual interrupt */ 163 and_b(~0x01, &TSR4); /* clear an eventual interrupt */
172 164
173 return true; 165 return true;
174#elif CONFIG_CPU == AS3525
175 if (start)
176 {
177 if (pfn_unregister != NULL)
178 {
179 pfn_unregister();
180 pfn_unregister = NULL;
181 }
182 }
183
184 TIMER1_LOAD = TIMER1_BGLOAD = cycles;
185 /* /!\ bit 4 (reserved) must not be modified
186 * periodic mode, interrupt enabled, no prescale, 32 bits counter */
187 TIMER1_CONTROL = (TIMER1_CONTROL & (1<<4)) |
188 TIMER_ENABLE |
189 TIMER_PERIODIC |
190 TIMER_INT_ENABLE |
191 TIMER_32_BIT;
192 return true;
193#elif defined CPU_COLDFIRE 166#elif defined CPU_COLDFIRE
194 if (prescale > 4096/CPUFREQ_MAX_MULT) 167 if (prescale > 4096/CPUFREQ_MAX_MULT)
195 return false; 168 return false;
@@ -314,10 +287,6 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
314 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR); 287 irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
315 irq_enable_int(IRQ_TIMER1); 288 irq_enable_int(IRQ_TIMER1);
316 return true; 289 return true;
317#elif CONFIG_CPU == AS3525
318 CGU_PERI |= CGU_TIMER1_CLOCK_ENABLE; /* enable peripheral */
319 VIC_INT_ENABLE |= INTERRUPT_TIMER1;
320 return true;
321#else 290#else
322 return __TIMER_REGISTER(reg_prio, unregister_callback, cycles, 291 return __TIMER_REGISTER(reg_prio, unregister_callback, cycles,
323 int_prio, timer_callback); 292 int_prio, timer_callback);
@@ -351,10 +320,6 @@ void timer_unregister(void)
351#elif CONFIG_CPU == PNX0101 320#elif CONFIG_CPU == PNX0101
352 TIMER1.ctrl &= ~0x80; /* disable timer 1 */ 321 TIMER1.ctrl &= ~0x80; /* disable timer 1 */
353 irq_disable_int(IRQ_TIMER1); 322 irq_disable_int(IRQ_TIMER1);
354#elif CONFIG_CPU == AS3525
355 TIMER1_CONTROL &= 0x10; /* disable timer 1 (don't modify bit 4) */
356 VIC_INT_EN_CLEAR = INTERRUPT_TIMER1; /* disable interrupt */
357 CGU_PERI &= ~CGU_TIMER1_CLOCK_ENABLE; /* disable peripheral */
358#else 323#else
359 __TIMER_UNREGISTER(); 324 __TIMER_UNREGISTER();
360#endif 325#endif