diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2009-02-23 04:33:33 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-02-23 04:33:33 +0000 |
commit | b1dccc47fd8488cef147961f247f0e34d57a0399 (patch) | |
tree | 0b712b361b8ac24cc49297c6878ff04238565ab6 /firmware/target | |
parent | 93f4bd351bcbd422d81592182aa1a2328f8d2d25 (diff) | |
download | rockbox-b1dccc47fd8488cef147961f247f0e34d57a0399.tar.gz rockbox-b1dccc47fd8488cef147961f247f0e34d57a0399.zip |
PP502x: Improve accuracy of header file. It looks as though DMA channels share the same interrupt enable (tested that 0 and 2 do at least).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20089 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/pcm-pp.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/arm/pcm-pp.c b/firmware/target/arm/pcm-pp.c index f441bb82ce..ce30908b0e 100644 --- a/firmware/target/arm/pcm-pp.c +++ b/firmware/target/arm/pcm-pp.c | |||
@@ -328,7 +328,7 @@ void pcm_play_lock(void) | |||
328 | 328 | ||
329 | if (++dma_play_data.locked == 1) { | 329 | if (++dma_play_data.locked == 1) { |
330 | #ifdef CPU_PP502x | 330 | #ifdef CPU_PP502x |
331 | CPU_INT_DIS = DMA0_MASK; | 331 | CPU_INT_DIS = DMA_MASK; |
332 | #else | 332 | #else |
333 | IIS_IRQTX_REG &= ~IIS_IRQTX; | 333 | IIS_IRQTX_REG &= ~IIS_IRQTX; |
334 | #endif | 334 | #endif |
@@ -343,7 +343,7 @@ void pcm_play_unlock(void) | |||
343 | 343 | ||
344 | if (--dma_play_data.locked == 0 && dma_play_data.state != 0) { | 344 | if (--dma_play_data.locked == 0 && dma_play_data.state != 0) { |
345 | #ifdef CPU_PP502x | 345 | #ifdef CPU_PP502x |
346 | CPU_INT_EN = DMA0_MASK; | 346 | CPU_INT_EN = DMA_MASK; |
347 | #else | 347 | #else |
348 | IIS_IRQTX_REG |= IIS_IRQTX; | 348 | IIS_IRQTX_REG |= IIS_IRQTX; |
349 | #endif | 349 | #endif |
@@ -493,8 +493,8 @@ void pcm_play_dma_init(void) | |||
493 | #ifdef CPU_PP502x | 493 | #ifdef CPU_PP502x |
494 | /* Enable DMA controller */ | 494 | /* Enable DMA controller */ |
495 | DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN; | 495 | DMA_MASTER_CONTROL |= DMA_MASTER_CONTROL_EN; |
496 | /* FIQ priority for DMA0 */ | 496 | /* FIQ priority for DMA */ |
497 | CPU_INT_PRIORITY |= DMA0_MASK; | 497 | CPU_INT_PRIORITY |= DMA_MASK; |
498 | /* Enable request?? Not setting or clearing everything doesn't seem to | 498 | /* Enable request?? Not setting or clearing everything doesn't seem to |
499 | * prevent it operating. Perhaps important for reliability (how requests | 499 | * prevent it operating. Perhaps important for reliability (how requests |
500 | * are handled). */ | 500 | * are handled). */ |