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author | Bertrik Sikken <bertrik@sikken.nl> | 2010-06-18 18:32:38 +0000 |
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committer | Bertrik Sikken <bertrik@sikken.nl> | 2010-06-18 18:32:38 +0000 |
commit | ae64b59afad9e186340b4cfe27f8fa78157c80b1 (patch) | |
tree | 8f619bd68868b2a2e5fc216cd0ef79fbefe42fd4 /firmware/target | |
parent | 3e690ac60d1d525e54f80cc6ece4d16e2cd9009f (diff) | |
download | rockbox-ae64b59afad9e186340b4cfe27f8fa78157c80b1.tar.gz rockbox-ae64b59afad9e186340b4cfe27f8fa78157c80b1.zip |
as3525v2: document PLL bits and show current PLL frequency in the debug menu
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26930 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 12 | ||||
-rw-r--r-- | firmware/target/arm/as3525/debug-as3525.c | 19 |
2 files changed, 27 insertions, 4 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 96c2c264fe..1689c59448 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -62,10 +62,20 @@ | |||
62 | #if CONFIG_CPU == AS3525v2 | 62 | #if CONFIG_CPU == AS3525v2 |
63 | 63 | ||
64 | /* PLLA & PLLB registers differ from AS3525(v1) | 64 | /* PLLA & PLLB registers differ from AS3525(v1) |
65 | * so we use a setting with a known frequency */ | 65 | * PLL bits: |
66 | * - bit 0-6 = F-1 (F=multiplier) | ||
67 | * - bit 7-9 = R-1 (R=divisor) | ||
68 | * - bit 10 = OD (output divider)? Divides by 2 if set. | ||
69 | * - bit 11 = unknown (no effect) | ||
70 | * - bit 12 = unknown (always set to 1) | ||
71 | * Fpll = Fin * F / (R * OD), where Fin = 12 MHz | ||
72 | */ | ||
66 | #define AS3525_PLLA_FREQ 240000000 | 73 | #define AS3525_PLLA_FREQ 240000000 |
67 | #define AS3525_PLLA_SETTING 0x113B | 74 | #define AS3525_PLLA_SETTING 0x113B |
68 | 75 | ||
76 | #define AS3525_PLLB_FREQ 192000000 | ||
77 | #define AS3525_PLLB_SETTING 0x155F | ||
78 | |||
69 | #define AS3525_FCLK_PREDIV 0 | 79 | #define AS3525_FCLK_PREDIV 0 |
70 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ | 80 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ |
71 | 81 | ||
diff --git a/firmware/target/arm/as3525/debug-as3525.c b/firmware/target/arm/as3525/debug-as3525.c index 2528b1a8ad..e6ae3a4a5d 100644 --- a/firmware/target/arm/as3525/debug-as3525.c +++ b/firmware/target/arm/as3525/debug-as3525.c | |||
@@ -112,14 +112,27 @@ static int calc_freq(int clk) | |||
112 | (((CGU_PLLB>>8) & 0x1f)*out_div); | 112 | (((CGU_PLLB>>8) & 0x1f)*out_div); |
113 | return 0; | 113 | return 0; |
114 | #else | 114 | #else |
115 | int od, f, r; | ||
116 | |||
115 | /* AS3525v2 */ | 117 | /* AS3525v2 */ |
116 | switch(clk) { | 118 | switch(clk) { |
117 | /* we're using a known setting for PLLA = 240 MHz and PLLB inop */ | ||
118 | case CLK_PLLA: | 119 | case CLK_PLLA: |
119 | return 240000000; | 120 | if(CGU_PLLASUP & (1<<3)) |
121 | return 0; | ||
122 | |||
123 | f = (CGU_PLLA & 0x7F) + 1; | ||
124 | r = ((CGU_PLLA >> 7) & 0x7) + 1; | ||
125 | od = (CGU_PLLA >> 10) & 1 ? 2 : 1; | ||
126 | return (CLK_MAIN / 2) * f / (r * od); | ||
120 | 127 | ||
121 | case CLK_PLLB: | 128 | case CLK_PLLB: |
122 | return 0; | 129 | if(CGU_PLLBSUP & (1<<3)) |
130 | return 0; | ||
131 | |||
132 | f = (CGU_PLLB & 0x7F) + 1; | ||
133 | r = ((CGU_PLLB >> 7) & 0x7) + 1; | ||
134 | od = (CGU_PLLB >> 10) & 1 ? 2 : 1; | ||
135 | return (CLK_MAIN / 2) * f / (r * od); | ||
123 | #endif | 136 | #endif |
124 | case CLK_PROC: | 137 | case CLK_PROC: |
125 | #if CONFIG_CPU == AS3525 /* not in arm926-ejs */ | 138 | #if CONFIG_CPU == AS3525 /* not in arm926-ejs */ |