diff options
Diffstat (limited to 'firmware/target/arm/as3525/clock-target.h')
-rw-r--r-- | firmware/target/arm/as3525/clock-target.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/firmware/target/arm/as3525/clock-target.h b/firmware/target/arm/as3525/clock-target.h index 96c2c264fe..1689c59448 100644 --- a/firmware/target/arm/as3525/clock-target.h +++ b/firmware/target/arm/as3525/clock-target.h | |||
@@ -62,10 +62,20 @@ | |||
62 | #if CONFIG_CPU == AS3525v2 | 62 | #if CONFIG_CPU == AS3525v2 |
63 | 63 | ||
64 | /* PLLA & PLLB registers differ from AS3525(v1) | 64 | /* PLLA & PLLB registers differ from AS3525(v1) |
65 | * so we use a setting with a known frequency */ | 65 | * PLL bits: |
66 | * - bit 0-6 = F-1 (F=multiplier) | ||
67 | * - bit 7-9 = R-1 (R=divisor) | ||
68 | * - bit 10 = OD (output divider)? Divides by 2 if set. | ||
69 | * - bit 11 = unknown (no effect) | ||
70 | * - bit 12 = unknown (always set to 1) | ||
71 | * Fpll = Fin * F / (R * OD), where Fin = 12 MHz | ||
72 | */ | ||
66 | #define AS3525_PLLA_FREQ 240000000 | 73 | #define AS3525_PLLA_FREQ 240000000 |
67 | #define AS3525_PLLA_SETTING 0x113B | 74 | #define AS3525_PLLA_SETTING 0x113B |
68 | 75 | ||
76 | #define AS3525_PLLB_FREQ 192000000 | ||
77 | #define AS3525_PLLB_SETTING 0x155F | ||
78 | |||
69 | #define AS3525_FCLK_PREDIV 0 | 79 | #define AS3525_FCLK_PREDIV 0 |
70 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ | 80 | #define AS3525_FCLK_FREQ AS3525_PLLA_FREQ |
71 | 81 | ||