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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-29 16:34:32 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-29 16:34:32 +0100 |
commit | f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf (patch) | |
tree | 7b919f493c0dc5263d7c2c91894fc26bc0503b30 /firmware/target/mips/ingenic_x1000/x1000/ssi.h | |
parent | 8056b7fd1a333fe4d0c7ed8d3de0caf702f89164 (diff) | |
download | rockbox-f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf.tar.gz rockbox-f64e8dc33c83e41f5ce3917ba1c88bcfbbb6a3bf.zip |
x1000: Complete the register definitions
I think this covers everything now, although some fields are missing
enum values. Those can be added in if and when they are needed.
Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/ssi.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/ssi.h | 323 |
1 files changed, 323 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ssi.h b/firmware/target/mips/ingenic_x1000/x1000/ssi.h new file mode 100644 index 0000000000..731e73c3a6 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ssi.h | |||
@@ -0,0 +1,323 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_SSI_H__ | ||
25 | #define __HEADERGEN_SSI_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_SSI_DR jz_reg(SSI_DR) | ||
30 | #define JA_SSI_DR (0xb0043000 + 0x0) | ||
31 | #define JT_SSI_DR JIO_32_RW | ||
32 | #define JN_SSI_DR SSI_DR | ||
33 | #define JI_SSI_DR | ||
34 | |||
35 | #define REG_SSI_CR0 jz_reg(SSI_CR0) | ||
36 | #define JA_SSI_CR0 (0xb0043000 + 0x4) | ||
37 | #define JT_SSI_CR0 JIO_32_RW | ||
38 | #define JN_SSI_CR0 SSI_CR0 | ||
39 | #define JI_SSI_CR0 | ||
40 | #define BP_SSI_CR0_TENDIAN 18 | ||
41 | #define BM_SSI_CR0_TENDIAN 0xc0000 | ||
42 | #define BF_SSI_CR0_TENDIAN(v) (((v) & 0x3) << 18) | ||
43 | #define BFM_SSI_CR0_TENDIAN(v) BM_SSI_CR0_TENDIAN | ||
44 | #define BF_SSI_CR0_TENDIAN_V(e) BF_SSI_CR0_TENDIAN(BV_SSI_CR0_TENDIAN__##e) | ||
45 | #define BFM_SSI_CR0_TENDIAN_V(v) BM_SSI_CR0_TENDIAN | ||
46 | #define BP_SSI_CR0_RENDIAN 16 | ||
47 | #define BM_SSI_CR0_RENDIAN 0x30000 | ||
48 | #define BF_SSI_CR0_RENDIAN(v) (((v) & 0x3) << 16) | ||
49 | #define BFM_SSI_CR0_RENDIAN(v) BM_SSI_CR0_RENDIAN | ||
50 | #define BF_SSI_CR0_RENDIAN_V(e) BF_SSI_CR0_RENDIAN(BV_SSI_CR0_RENDIAN__##e) | ||
51 | #define BFM_SSI_CR0_RENDIAN_V(v) BM_SSI_CR0_RENDIAN | ||
52 | #define BP_SSI_CR0_SSIE 15 | ||
53 | #define BM_SSI_CR0_SSIE 0x8000 | ||
54 | #define BF_SSI_CR0_SSIE(v) (((v) & 0x1) << 15) | ||
55 | #define BFM_SSI_CR0_SSIE(v) BM_SSI_CR0_SSIE | ||
56 | #define BF_SSI_CR0_SSIE_V(e) BF_SSI_CR0_SSIE(BV_SSI_CR0_SSIE__##e) | ||
57 | #define BFM_SSI_CR0_SSIE_V(v) BM_SSI_CR0_SSIE | ||
58 | #define BP_SSI_CR0_TIE 14 | ||
59 | #define BM_SSI_CR0_TIE 0x4000 | ||
60 | #define BF_SSI_CR0_TIE(v) (((v) & 0x1) << 14) | ||
61 | #define BFM_SSI_CR0_TIE(v) BM_SSI_CR0_TIE | ||
62 | #define BF_SSI_CR0_TIE_V(e) BF_SSI_CR0_TIE(BV_SSI_CR0_TIE__##e) | ||
63 | #define BFM_SSI_CR0_TIE_V(v) BM_SSI_CR0_TIE | ||
64 | #define BP_SSI_CR0_RIE 13 | ||
65 | #define BM_SSI_CR0_RIE 0x2000 | ||
66 | #define BF_SSI_CR0_RIE(v) (((v) & 0x1) << 13) | ||
67 | #define BFM_SSI_CR0_RIE(v) BM_SSI_CR0_RIE | ||
68 | #define BF_SSI_CR0_RIE_V(e) BF_SSI_CR0_RIE(BV_SSI_CR0_RIE__##e) | ||
69 | #define BFM_SSI_CR0_RIE_V(v) BM_SSI_CR0_RIE | ||
70 | #define BP_SSI_CR0_TEIE 12 | ||
71 | #define BM_SSI_CR0_TEIE 0x1000 | ||
72 | #define BF_SSI_CR0_TEIE(v) (((v) & 0x1) << 12) | ||
73 | #define BFM_SSI_CR0_TEIE(v) BM_SSI_CR0_TEIE | ||
74 | #define BF_SSI_CR0_TEIE_V(e) BF_SSI_CR0_TEIE(BV_SSI_CR0_TEIE__##e) | ||
75 | #define BFM_SSI_CR0_TEIE_V(v) BM_SSI_CR0_TEIE | ||
76 | #define BP_SSI_CR0_REIE 11 | ||
77 | #define BM_SSI_CR0_REIE 0x800 | ||
78 | #define BF_SSI_CR0_REIE(v) (((v) & 0x1) << 11) | ||
79 | #define BFM_SSI_CR0_REIE(v) BM_SSI_CR0_REIE | ||
80 | #define BF_SSI_CR0_REIE_V(e) BF_SSI_CR0_REIE(BV_SSI_CR0_REIE__##e) | ||
81 | #define BFM_SSI_CR0_REIE_V(v) BM_SSI_CR0_REIE | ||
82 | #define BP_SSI_CR0_LOOP 10 | ||
83 | #define BM_SSI_CR0_LOOP 0x400 | ||
84 | #define BF_SSI_CR0_LOOP(v) (((v) & 0x1) << 10) | ||
85 | #define BFM_SSI_CR0_LOOP(v) BM_SSI_CR0_LOOP | ||
86 | #define BF_SSI_CR0_LOOP_V(e) BF_SSI_CR0_LOOP(BV_SSI_CR0_LOOP__##e) | ||
87 | #define BFM_SSI_CR0_LOOP_V(v) BM_SSI_CR0_LOOP | ||
88 | #define BP_SSI_CR0_RFINE 9 | ||
89 | #define BM_SSI_CR0_RFINE 0x200 | ||
90 | #define BF_SSI_CR0_RFINE(v) (((v) & 0x1) << 9) | ||
91 | #define BFM_SSI_CR0_RFINE(v) BM_SSI_CR0_RFINE | ||
92 | #define BF_SSI_CR0_RFINE_V(e) BF_SSI_CR0_RFINE(BV_SSI_CR0_RFINE__##e) | ||
93 | #define BFM_SSI_CR0_RFINE_V(v) BM_SSI_CR0_RFINE | ||
94 | #define BP_SSI_CR0_RFINC 8 | ||
95 | #define BM_SSI_CR0_RFINC 0x100 | ||
96 | #define BF_SSI_CR0_RFINC(v) (((v) & 0x1) << 8) | ||
97 | #define BFM_SSI_CR0_RFINC(v) BM_SSI_CR0_RFINC | ||
98 | #define BF_SSI_CR0_RFINC_V(e) BF_SSI_CR0_RFINC(BV_SSI_CR0_RFINC__##e) | ||
99 | #define BFM_SSI_CR0_RFINC_V(v) BM_SSI_CR0_RFINC | ||
100 | #define BP_SSI_CR0_EACLRUN 7 | ||
101 | #define BM_SSI_CR0_EACLRUN 0x80 | ||
102 | #define BF_SSI_CR0_EACLRUN(v) (((v) & 0x1) << 7) | ||
103 | #define BFM_SSI_CR0_EACLRUN(v) BM_SSI_CR0_EACLRUN | ||
104 | #define BF_SSI_CR0_EACLRUN_V(e) BF_SSI_CR0_EACLRUN(BV_SSI_CR0_EACLRUN__##e) | ||
105 | #define BFM_SSI_CR0_EACLRUN_V(v) BM_SSI_CR0_EACLRUN | ||
106 | #define BP_SSI_CR0_FSEL 6 | ||
107 | #define BM_SSI_CR0_FSEL 0x40 | ||
108 | #define BF_SSI_CR0_FSEL(v) (((v) & 0x1) << 6) | ||
109 | #define BFM_SSI_CR0_FSEL(v) BM_SSI_CR0_FSEL | ||
110 | #define BF_SSI_CR0_FSEL_V(e) BF_SSI_CR0_FSEL(BV_SSI_CR0_FSEL__##e) | ||
111 | #define BFM_SSI_CR0_FSEL_V(v) BM_SSI_CR0_FSEL | ||
112 | #define BP_SSI_CR0_VRCNT 4 | ||
113 | #define BM_SSI_CR0_VRCNT 0x10 | ||
114 | #define BF_SSI_CR0_VRCNT(v) (((v) & 0x1) << 4) | ||
115 | #define BFM_SSI_CR0_VRCNT(v) BM_SSI_CR0_VRCNT | ||
116 | #define BF_SSI_CR0_VRCNT_V(e) BF_SSI_CR0_VRCNT(BV_SSI_CR0_VRCNT__##e) | ||
117 | #define BFM_SSI_CR0_VRCNT_V(v) BM_SSI_CR0_VRCNT | ||
118 | #define BP_SSI_CR0_TFMODE 3 | ||
119 | #define BM_SSI_CR0_TFMODE 0x8 | ||
120 | #define BF_SSI_CR0_TFMODE(v) (((v) & 0x1) << 3) | ||
121 | #define BFM_SSI_CR0_TFMODE(v) BM_SSI_CR0_TFMODE | ||
122 | #define BF_SSI_CR0_TFMODE_V(e) BF_SSI_CR0_TFMODE(BV_SSI_CR0_TFMODE__##e) | ||
123 | #define BFM_SSI_CR0_TFMODE_V(v) BM_SSI_CR0_TFMODE | ||
124 | #define BP_SSI_CR0_TFLUSH 2 | ||
125 | #define BM_SSI_CR0_TFLUSH 0x4 | ||
126 | #define BF_SSI_CR0_TFLUSH(v) (((v) & 0x1) << 2) | ||
127 | #define BFM_SSI_CR0_TFLUSH(v) BM_SSI_CR0_TFLUSH | ||
128 | #define BF_SSI_CR0_TFLUSH_V(e) BF_SSI_CR0_TFLUSH(BV_SSI_CR0_TFLUSH__##e) | ||
129 | #define BFM_SSI_CR0_TFLUSH_V(v) BM_SSI_CR0_TFLUSH | ||
130 | #define BP_SSI_CR0_RFLUSH 1 | ||
131 | #define BM_SSI_CR0_RFLUSH 0x2 | ||
132 | #define BF_SSI_CR0_RFLUSH(v) (((v) & 0x1) << 1) | ||
133 | #define BFM_SSI_CR0_RFLUSH(v) BM_SSI_CR0_RFLUSH | ||
134 | #define BF_SSI_CR0_RFLUSH_V(e) BF_SSI_CR0_RFLUSH(BV_SSI_CR0_RFLUSH__##e) | ||
135 | #define BFM_SSI_CR0_RFLUSH_V(v) BM_SSI_CR0_RFLUSH | ||
136 | #define BP_SSI_CR0_DISREV 0 | ||
137 | #define BM_SSI_CR0_DISREV 0x1 | ||
138 | #define BF_SSI_CR0_DISREV(v) (((v) & 0x1) << 0) | ||
139 | #define BFM_SSI_CR0_DISREV(v) BM_SSI_CR0_DISREV | ||
140 | #define BF_SSI_CR0_DISREV_V(e) BF_SSI_CR0_DISREV(BV_SSI_CR0_DISREV__##e) | ||
141 | #define BFM_SSI_CR0_DISREV_V(v) BM_SSI_CR0_DISREV | ||
142 | |||
143 | #define REG_SSI_CR1 jz_reg(SSI_CR1) | ||
144 | #define JA_SSI_CR1 (0xb0043000 + 0x8) | ||
145 | #define JT_SSI_CR1 JIO_32_RW | ||
146 | #define JN_SSI_CR1 SSI_CR1 | ||
147 | #define JI_SSI_CR1 | ||
148 | #define BP_SSI_CR1_FRMHL 30 | ||
149 | #define BM_SSI_CR1_FRMHL 0xc0000000 | ||
150 | #define BF_SSI_CR1_FRMHL(v) (((v) & 0x3) << 30) | ||
151 | #define BFM_SSI_CR1_FRMHL(v) BM_SSI_CR1_FRMHL | ||
152 | #define BF_SSI_CR1_FRMHL_V(e) BF_SSI_CR1_FRMHL(BV_SSI_CR1_FRMHL__##e) | ||
153 | #define BFM_SSI_CR1_FRMHL_V(v) BM_SSI_CR1_FRMHL | ||
154 | #define BP_SSI_CR1_TFVCK 28 | ||
155 | #define BM_SSI_CR1_TFVCK 0x30000000 | ||
156 | #define BF_SSI_CR1_TFVCK(v) (((v) & 0x3) << 28) | ||
157 | #define BFM_SSI_CR1_TFVCK(v) BM_SSI_CR1_TFVCK | ||
158 | #define BF_SSI_CR1_TFVCK_V(e) BF_SSI_CR1_TFVCK(BV_SSI_CR1_TFVCK__##e) | ||
159 | #define BFM_SSI_CR1_TFVCK_V(v) BM_SSI_CR1_TFVCK | ||
160 | #define BP_SSI_CR1_TCKFI 26 | ||
161 | #define BM_SSI_CR1_TCKFI 0xc000000 | ||
162 | #define BF_SSI_CR1_TCKFI(v) (((v) & 0x3) << 26) | ||
163 | #define BFM_SSI_CR1_TCKFI(v) BM_SSI_CR1_TCKFI | ||
164 | #define BF_SSI_CR1_TCKFI_V(e) BF_SSI_CR1_TCKFI(BV_SSI_CR1_TCKFI__##e) | ||
165 | #define BFM_SSI_CR1_TCKFI_V(v) BM_SSI_CR1_TCKFI | ||
166 | #define BP_SSI_CR1_FMAT 20 | ||
167 | #define BM_SSI_CR1_FMAT 0x300000 | ||
168 | #define BF_SSI_CR1_FMAT(v) (((v) & 0x3) << 20) | ||
169 | #define BFM_SSI_CR1_FMAT(v) BM_SSI_CR1_FMAT | ||
170 | #define BF_SSI_CR1_FMAT_V(e) BF_SSI_CR1_FMAT(BV_SSI_CR1_FMAT__##e) | ||
171 | #define BFM_SSI_CR1_FMAT_V(v) BM_SSI_CR1_FMAT | ||
172 | #define BP_SSI_CR1_TTRG 16 | ||
173 | #define BM_SSI_CR1_TTRG 0xf0000 | ||
174 | #define BF_SSI_CR1_TTRG(v) (((v) & 0xf) << 16) | ||
175 | #define BFM_SSI_CR1_TTRG(v) BM_SSI_CR1_TTRG | ||
176 | #define BF_SSI_CR1_TTRG_V(e) BF_SSI_CR1_TTRG(BV_SSI_CR1_TTRG__##e) | ||
177 | #define BFM_SSI_CR1_TTRG_V(v) BM_SSI_CR1_TTRG | ||
178 | #define BP_SSI_CR1_MCOM 12 | ||
179 | #define BM_SSI_CR1_MCOM 0xf000 | ||
180 | #define BF_SSI_CR1_MCOM(v) (((v) & 0xf) << 12) | ||
181 | #define BFM_SSI_CR1_MCOM(v) BM_SSI_CR1_MCOM | ||
182 | #define BF_SSI_CR1_MCOM_V(e) BF_SSI_CR1_MCOM(BV_SSI_CR1_MCOM__##e) | ||
183 | #define BFM_SSI_CR1_MCOM_V(v) BM_SSI_CR1_MCOM | ||
184 | #define BP_SSI_CR1_RTRG 8 | ||
185 | #define BM_SSI_CR1_RTRG 0xf00 | ||
186 | #define BF_SSI_CR1_RTRG(v) (((v) & 0xf) << 8) | ||
187 | #define BFM_SSI_CR1_RTRG(v) BM_SSI_CR1_RTRG | ||
188 | #define BF_SSI_CR1_RTRG_V(e) BF_SSI_CR1_RTRG(BV_SSI_CR1_RTRG__##e) | ||
189 | #define BFM_SSI_CR1_RTRG_V(v) BM_SSI_CR1_RTRG | ||
190 | #define BP_SSI_CR1_FLEN 3 | ||
191 | #define BM_SSI_CR1_FLEN 0xf8 | ||
192 | #define BF_SSI_CR1_FLEN(v) (((v) & 0x1f) << 3) | ||
193 | #define BFM_SSI_CR1_FLEN(v) BM_SSI_CR1_FLEN | ||
194 | #define BF_SSI_CR1_FLEN_V(e) BF_SSI_CR1_FLEN(BV_SSI_CR1_FLEN__##e) | ||
195 | #define BFM_SSI_CR1_FLEN_V(v) BM_SSI_CR1_FLEN | ||
196 | #define BP_SSI_CR1_ITFRM 24 | ||
197 | #define BM_SSI_CR1_ITFRM 0x1000000 | ||
198 | #define BF_SSI_CR1_ITFRM(v) (((v) & 0x1) << 24) | ||
199 | #define BFM_SSI_CR1_ITFRM(v) BM_SSI_CR1_ITFRM | ||
200 | #define BF_SSI_CR1_ITFRM_V(e) BF_SSI_CR1_ITFRM(BV_SSI_CR1_ITFRM__##e) | ||
201 | #define BFM_SSI_CR1_ITFRM_V(v) BM_SSI_CR1_ITFRM | ||
202 | #define BP_SSI_CR1_UNFIN 23 | ||
203 | #define BM_SSI_CR1_UNFIN 0x800000 | ||
204 | #define BF_SSI_CR1_UNFIN(v) (((v) & 0x1) << 23) | ||
205 | #define BFM_SSI_CR1_UNFIN(v) BM_SSI_CR1_UNFIN | ||
206 | #define BF_SSI_CR1_UNFIN_V(e) BF_SSI_CR1_UNFIN(BV_SSI_CR1_UNFIN__##e) | ||
207 | #define BFM_SSI_CR1_UNFIN_V(v) BM_SSI_CR1_UNFIN | ||
208 | #define BP_SSI_CR1_PHA 1 | ||
209 | #define BM_SSI_CR1_PHA 0x2 | ||
210 | #define BF_SSI_CR1_PHA(v) (((v) & 0x1) << 1) | ||
211 | #define BFM_SSI_CR1_PHA(v) BM_SSI_CR1_PHA | ||
212 | #define BF_SSI_CR1_PHA_V(e) BF_SSI_CR1_PHA(BV_SSI_CR1_PHA__##e) | ||
213 | #define BFM_SSI_CR1_PHA_V(v) BM_SSI_CR1_PHA | ||
214 | #define BP_SSI_CR1_POL 0 | ||
215 | #define BM_SSI_CR1_POL 0x1 | ||
216 | #define BF_SSI_CR1_POL(v) (((v) & 0x1) << 0) | ||
217 | #define BFM_SSI_CR1_POL(v) BM_SSI_CR1_POL | ||
218 | #define BF_SSI_CR1_POL_V(e) BF_SSI_CR1_POL(BV_SSI_CR1_POL__##e) | ||
219 | #define BFM_SSI_CR1_POL_V(v) BM_SSI_CR1_POL | ||
220 | |||
221 | #define REG_SSI_SR jz_reg(SSI_SR) | ||
222 | #define JA_SSI_SR (0xb0043000 + 0xc) | ||
223 | #define JT_SSI_SR JIO_32_RW | ||
224 | #define JN_SSI_SR SSI_SR | ||
225 | #define JI_SSI_SR | ||
226 | #define BP_SSI_SR_TFIFO_NUM 16 | ||
227 | #define BM_SSI_SR_TFIFO_NUM 0x1ff0000 | ||
228 | #define BF_SSI_SR_TFIFO_NUM(v) (((v) & 0x1ff) << 16) | ||
229 | #define BFM_SSI_SR_TFIFO_NUM(v) BM_SSI_SR_TFIFO_NUM | ||
230 | #define BF_SSI_SR_TFIFO_NUM_V(e) BF_SSI_SR_TFIFO_NUM(BV_SSI_SR_TFIFO_NUM__##e) | ||
231 | #define BFM_SSI_SR_TFIFO_NUM_V(v) BM_SSI_SR_TFIFO_NUM | ||
232 | #define BP_SSI_SR_RFIFO_NUM 8 | ||
233 | #define BM_SSI_SR_RFIFO_NUM 0xff00 | ||
234 | #define BF_SSI_SR_RFIFO_NUM(v) (((v) & 0xff) << 8) | ||
235 | #define BFM_SSI_SR_RFIFO_NUM(v) BM_SSI_SR_RFIFO_NUM | ||
236 | #define BF_SSI_SR_RFIFO_NUM_V(e) BF_SSI_SR_RFIFO_NUM(BV_SSI_SR_RFIFO_NUM__##e) | ||
237 | #define BFM_SSI_SR_RFIFO_NUM_V(v) BM_SSI_SR_RFIFO_NUM | ||
238 | #define BP_SSI_SR_END 7 | ||
239 | #define BM_SSI_SR_END 0x80 | ||
240 | #define BF_SSI_SR_END(v) (((v) & 0x1) << 7) | ||
241 | #define BFM_SSI_SR_END(v) BM_SSI_SR_END | ||
242 | #define BF_SSI_SR_END_V(e) BF_SSI_SR_END(BV_SSI_SR_END__##e) | ||
243 | #define BFM_SSI_SR_END_V(v) BM_SSI_SR_END | ||
244 | #define BP_SSI_SR_BUSY 6 | ||
245 | #define BM_SSI_SR_BUSY 0x40 | ||
246 | #define BF_SSI_SR_BUSY(v) (((v) & 0x1) << 6) | ||
247 | #define BFM_SSI_SR_BUSY(v) BM_SSI_SR_BUSY | ||
248 | #define BF_SSI_SR_BUSY_V(e) BF_SSI_SR_BUSY(BV_SSI_SR_BUSY__##e) | ||
249 | #define BFM_SSI_SR_BUSY_V(v) BM_SSI_SR_BUSY | ||
250 | #define BP_SSI_SR_TFF 5 | ||
251 | #define BM_SSI_SR_TFF 0x20 | ||
252 | #define BF_SSI_SR_TFF(v) (((v) & 0x1) << 5) | ||
253 | #define BFM_SSI_SR_TFF(v) BM_SSI_SR_TFF | ||
254 | #define BF_SSI_SR_TFF_V(e) BF_SSI_SR_TFF(BV_SSI_SR_TFF__##e) | ||
255 | #define BFM_SSI_SR_TFF_V(v) BM_SSI_SR_TFF | ||
256 | #define BP_SSI_SR_RFE 4 | ||
257 | #define BM_SSI_SR_RFE 0x10 | ||
258 | #define BF_SSI_SR_RFE(v) (((v) & 0x1) << 4) | ||
259 | #define BFM_SSI_SR_RFE(v) BM_SSI_SR_RFE | ||
260 | #define BF_SSI_SR_RFE_V(e) BF_SSI_SR_RFE(BV_SSI_SR_RFE__##e) | ||
261 | #define BFM_SSI_SR_RFE_V(v) BM_SSI_SR_RFE | ||
262 | #define BP_SSI_SR_TFHE 3 | ||
263 | #define BM_SSI_SR_TFHE 0x8 | ||
264 | #define BF_SSI_SR_TFHE(v) (((v) & 0x1) << 3) | ||
265 | #define BFM_SSI_SR_TFHE(v) BM_SSI_SR_TFHE | ||
266 | #define BF_SSI_SR_TFHE_V(e) BF_SSI_SR_TFHE(BV_SSI_SR_TFHE__##e) | ||
267 | #define BFM_SSI_SR_TFHE_V(v) BM_SSI_SR_TFHE | ||
268 | #define BP_SSI_SR_RFHF 2 | ||
269 | #define BM_SSI_SR_RFHF 0x4 | ||
270 | #define BF_SSI_SR_RFHF(v) (((v) & 0x1) << 2) | ||
271 | #define BFM_SSI_SR_RFHF(v) BM_SSI_SR_RFHF | ||
272 | #define BF_SSI_SR_RFHF_V(e) BF_SSI_SR_RFHF(BV_SSI_SR_RFHF__##e) | ||
273 | #define BFM_SSI_SR_RFHF_V(v) BM_SSI_SR_RFHF | ||
274 | #define BP_SSI_SR_UNDR 1 | ||
275 | #define BM_SSI_SR_UNDR 0x2 | ||
276 | #define BF_SSI_SR_UNDR(v) (((v) & 0x1) << 1) | ||
277 | #define BFM_SSI_SR_UNDR(v) BM_SSI_SR_UNDR | ||
278 | #define BF_SSI_SR_UNDR_V(e) BF_SSI_SR_UNDR(BV_SSI_SR_UNDR__##e) | ||
279 | #define BFM_SSI_SR_UNDR_V(v) BM_SSI_SR_UNDR | ||
280 | #define BP_SSI_SR_OVER 0 | ||
281 | #define BM_SSI_SR_OVER 0x1 | ||
282 | #define BF_SSI_SR_OVER(v) (((v) & 0x1) << 0) | ||
283 | #define BFM_SSI_SR_OVER(v) BM_SSI_SR_OVER | ||
284 | #define BF_SSI_SR_OVER_V(e) BF_SSI_SR_OVER(BV_SSI_SR_OVER__##e) | ||
285 | #define BFM_SSI_SR_OVER_V(v) BM_SSI_SR_OVER | ||
286 | |||
287 | #define REG_SSI_ITR jz_reg(SSI_ITR) | ||
288 | #define JA_SSI_ITR (0xb0043000 + 0x10) | ||
289 | #define JT_SSI_ITR JIO_32_RW | ||
290 | #define JN_SSI_ITR SSI_ITR | ||
291 | #define JI_SSI_ITR | ||
292 | #define BP_SSI_ITR_IVLTM 0 | ||
293 | #define BM_SSI_ITR_IVLTM 0x7fff | ||
294 | #define BF_SSI_ITR_IVLTM(v) (((v) & 0x7fff) << 0) | ||
295 | #define BFM_SSI_ITR_IVLTM(v) BM_SSI_ITR_IVLTM | ||
296 | #define BF_SSI_ITR_IVLTM_V(e) BF_SSI_ITR_IVLTM(BV_SSI_ITR_IVLTM__##e) | ||
297 | #define BFM_SSI_ITR_IVLTM_V(v) BM_SSI_ITR_IVLTM | ||
298 | #define BP_SSI_ITR_CNTCLK 15 | ||
299 | #define BM_SSI_ITR_CNTCLK 0x8000 | ||
300 | #define BF_SSI_ITR_CNTCLK(v) (((v) & 0x1) << 15) | ||
301 | #define BFM_SSI_ITR_CNTCLK(v) BM_SSI_ITR_CNTCLK | ||
302 | #define BF_SSI_ITR_CNTCLK_V(e) BF_SSI_ITR_CNTCLK(BV_SSI_ITR_CNTCLK__##e) | ||
303 | #define BFM_SSI_ITR_CNTCLK_V(v) BM_SSI_ITR_CNTCLK | ||
304 | |||
305 | #define REG_SSI_ICR jz_reg(SSI_ICR) | ||
306 | #define JA_SSI_ICR (0xb0043000 + 0x14) | ||
307 | #define JT_SSI_ICR JIO_32_RW | ||
308 | #define JN_SSI_ICR SSI_ICR | ||
309 | #define JI_SSI_ICR | ||
310 | |||
311 | #define REG_SSI_GR jz_reg(SSI_GR) | ||
312 | #define JA_SSI_GR (0xb0043000 + 0x18) | ||
313 | #define JT_SSI_GR JIO_32_RW | ||
314 | #define JN_SSI_GR SSI_GR | ||
315 | #define JI_SSI_GR | ||
316 | |||
317 | #define REG_SSI_RCNT jz_reg(SSI_RCNT) | ||
318 | #define JA_SSI_RCNT (0xb0043000 + 0x1c) | ||
319 | #define JT_SSI_RCNT JIO_32_RW | ||
320 | #define JN_SSI_RCNT SSI_RCNT | ||
321 | #define JI_SSI_RCNT | ||
322 | |||
323 | #endif /* __HEADERGEN_SSI_H__*/ | ||