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author | Dana Conrad <dconrad@fastmail.com> | 2021-06-26 12:07:11 -0500 |
---|---|---|
committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-07-18 12:14:35 +0000 |
commit | 3e7a09cb0dee0ee04b5c77f427bf89d990ec8d0b (patch) | |
tree | be1eb7e1d4166f60b245a0603e9f7dc11e1f5614 /firmware/target/mips/ingenic_x1000/clk-x1000.c | |
parent | 64a24591aec049682167b193700a07572fc04c4c (diff) | |
download | rockbox-3e7a09cb0dee0ee04b5c77f427bf89d990ec8d0b.tar.gz rockbox-3e7a09cb0dee0ee04b5c77f427bf89d990ec8d0b.zip |
New Port: Eros Q Native
What works:
- LCD: 16-bit RGB565
- all buttons, including scrollwheel
- SD Card
- Battery level and charging/not charging status
- USB
- audio
- sample rate switching
- HP / LO detect, with "safe" fixed LO volume -
LO volume will only be put to user-defined max volume
if headphones are not present.
- rtc
- Plugins build, tried a couple and they seem OK
- Bootloader, installable to nand via usbboot
What doesn't work:
- Dual Boot
- power on/off has intermittent, low volume audio click
(sometimes it's completely silent, sometimes there's
a click)
- Audio uses 16-bit volume scaling, so clicking/popping
is pretty bad at lower volumes - need 32 bit volume
scaling, 24 bit I2S data
- USB HID keys not yet defined
- no jztool support
Unknowns:
- Stereo Switch pins: Direction select, AC_DC
(probably not even hooked up)
- What is the actual purpose of the Stereo Swtich?
- How does the bluetooth module connect?
"Someday" stuff:
- get LCD working at higher bit depth
- Bluetooth
Change-Id: I70dda8fc092c6e3f4352f2245e4164193f803c33
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/clk-x1000.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/clk-x1000.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_x1000/clk-x1000.c b/firmware/target/mips/ingenic_x1000/clk-x1000.c index 7e254401fb..4988e7c3bf 100644 --- a/firmware/target/mips/ingenic_x1000/clk-x1000.c +++ b/firmware/target/mips/ingenic_x1000/clk-x1000.c | |||
@@ -265,7 +265,7 @@ void clk_init(void) | |||
265 | jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1)); | 265 | jz_writef(CPM_APCR, BS(1), PLLM(42 - 1), PLLN(0), PLLOD(0), ENABLE(1)); |
266 | while(jz_readf(CPM_APCR, ON) == 0); | 266 | while(jz_readf(CPM_APCR, ON) == 0); |
267 | 267 | ||
268 | #if defined(FIIO_M3K) | 268 | #if (defined(FIIO_M3K) || defined(EROS_QN)) |
269 | /* TODO: Allow targets to define their clock frequencies in their config, | 269 | /* TODO: Allow targets to define their clock frequencies in their config, |
270 | * instead of having this be a random special case. */ | 270 | * instead of having this be a random special case. */ |
271 | if(get_boot_option() == BOOT_OPTION_ROCKBOX) { | 271 | if(get_boot_option() == BOOT_OPTION_ROCKBOX) { |
@@ -296,7 +296,7 @@ void clk_init(void) | |||
296 | CLKMUX_CPU(SCLK_A) | | 296 | CLKMUX_CPU(SCLK_A) | |
297 | CLKMUX_AHB0(MPLL) | | 297 | CLKMUX_AHB0(MPLL) | |
298 | CLKMUX_AHB2(MPLL)); | 298 | CLKMUX_AHB2(MPLL)); |
299 | #if defined(FIIO_M3K) | 299 | #if (defined(FIIO_M3K) || defined(EROS_QN)) |
300 | } | 300 | } |
301 | #endif | 301 | #endif |
302 | 302 | ||