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authorWilliam Wilgus <wilgus.william@gmail.com>2020-08-27 10:06:19 -0400
committerWilliam Wilgus <me.theuser@yahoo.com>2020-08-27 14:33:23 +0000
commit5fb4c74bfb16f2dcf1249b04c491526ca89b1fad (patch)
tree7e8311b1fda6b76bd473ea32fdfbd34a1cfbd3ab /firmware/target/mips/ingenic_jz47xx
parent8990c90b874de947f0f9656ae94e91f2590b4d03 (diff)
downloadrockbox-5fb4c74bfb16f2dcf1249b04c491526ca89b1fad.tar.gz
rockbox-5fb4c74bfb16f2dcf1249b04c491526ca89b1fad.zip
Xduoo X3 - Grey scale lib update
greylib on the xduoo x3 now matches the rest of the 1bit targets Change-Id: I2685869da6734404356552cc9f4ed5f59ebd6650
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c39
1 files changed, 20 insertions, 19 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
index 89251b727d..ea29ce266d 100644
--- a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
+++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c
@@ -301,28 +301,29 @@ void lcd_blit_mono(const unsigned char *data, int x, int by, int width,
301void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) ICODE_ATTR; 301void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) ICODE_ATTR;
302void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) 302void lcd_grey_data(unsigned char *values, unsigned char *phases, int count)
303{ 303{
304 unsigned char a, b, c, d; 304 unsigned long ltmp;
305 unsigned long *lval = (unsigned long *)values;
306 unsigned long *lpha = (unsigned long *)phases;
307 const unsigned long mask = 0x80808080;
305 308
306 __gpio_set_pin(PIN_LCD_DC);
307 while(count--) 309 while(count--)
308 { 310 {
309 c = 0; 311 /* calculate disp data from phase we only use the last byte (8bits) */
310 d = 8; 312 ltmp = mask & lpha[0]; // ltmp= 3.......2.......1.......0.......
311 while(d--) 313 ltmp |= (mask & lpha[1]) >> 4; // ltmp= 7.......6.......5.......4.......
312 { 314 /* phase0 | phase1 >> 4 */ // ltmp= 3...7...2...6...1...5...0...4...
313 a = *phases; 315 ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..12..56..01..45..
314 b = *values++; 316 ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..123.567.012.456.
315 b += a & ~0x80; 317 ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..123.567.01234567
316 *phases++ = b; 318
317 c <<= 1; 319 /* update the phases */
318 c |= a >> 7; 320 lpha[0] = lval[0] + (lpha[0] & ~mask);
319 } 321 lpha[1] = lval[1] + (lpha[1] & ~mask);
320 REG_GPIO_PXDATC(2) = 0x000030FC; 322
321 REG_GPIO_PXDATS(2) = ((c & 0xC0) << 6) | ((c & 0x3F) << 2); 323 lcd_write_data((const fb_data*) &ltmp, 1);
322 __gpio_clear_pin(PIN_LCD_WR); 324
323 bitdelay(); 325 lpha+=2;
324 __gpio_set_pin(PIN_LCD_WR); 326 lval+=2;
325 bitdelay();
326 } 327 }
327} 328}
328 329