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author | William Wilgus <wilgus.william@gmail.com> | 2020-08-27 10:06:19 -0400 |
---|---|---|
committer | William Wilgus <me.theuser@yahoo.com> | 2020-08-27 14:33:23 +0000 |
commit | 5fb4c74bfb16f2dcf1249b04c491526ca89b1fad (patch) | |
tree | 7e8311b1fda6b76bd473ea32fdfbd34a1cfbd3ab | |
parent | 8990c90b874de947f0f9656ae94e91f2590b4d03 (diff) | |
download | rockbox-5fb4c74bfb16f2dcf1249b04c491526ca89b1fad.tar.gz rockbox-5fb4c74bfb16f2dcf1249b04c491526ca89b1fad.zip |
Xduoo X3 - Grey scale lib update
greylib on the xduoo x3 now matches the rest of the 1bit targets
Change-Id: I2685869da6734404356552cc9f4ed5f59ebd6650
-rw-r--r-- | firmware/export/jz4760b.h | 50 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c | 39 |
2 files changed, 45 insertions, 44 deletions
diff --git a/firmware/export/jz4760b.h b/firmware/export/jz4760b.h index c35e26767f..be1e4f3aea 100644 --- a/firmware/export/jz4760b.h +++ b/firmware/export/jz4760b.h | |||
@@ -242,31 +242,31 @@ | |||
242 | #ifndef __MIPS_ASSEMBLER | 242 | #ifndef __MIPS_ASSEMBLER |
243 | 243 | ||
244 | //n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF) | 244 | //n = 0,1,2,3,4,5 (PORTA, PORTB, PORTC, PORTD, PORTE, PORTF) |
245 | #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN(n)) | 245 | #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN(n)) /* PIN Level Register */ |
246 | #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT(n)) | 246 | #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT(n)) /* Port Data Register */ |
247 | #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS(n)) | 247 | #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS(n)) /* Port Data Set Register */ |
248 | #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC(n)) | 248 | #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC(n)) /* Port Data Clear Register */ |
249 | #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM(n)) | 249 | #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM(n)) /* Interrupt Mask Register */ |
250 | #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS(n)) | 250 | #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS(n)) /* Interrupt Mask Set Reg */ |
251 | #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC(n)) | 251 | #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC(n)) /* Interrupt Mask Clear Reg */ |
252 | #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE(n)) | 252 | #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE(n)) /* Pull Enable Register */ |
253 | #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES(n)) | 253 | #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES(n)) /* Pull Enable Set Register */ |
254 | #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC(n)) | 254 | #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC(n)) /* Pull Enable Clear Register */ |
255 | #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN(n)) | 255 | #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN(n)) /* Function Register */ |
256 | #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS(n)) | 256 | #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS(n)) /* Function Set Register */ |
257 | #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC(n)) | 257 | #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC(n)) /* Function Clear Register */ |
258 | #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL(n)) | 258 | #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL(n)) /* Select Register */ |
259 | #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS(n)) | 259 | #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS(n)) /* Select Set Register */ |
260 | #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC(n)) | 260 | #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC(n)) /* Select Clear Register */ |
261 | #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR(n)) | 261 | #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR(n)) /* Direction Register */ |
262 | #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS(n)) | 262 | #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS(n)) /* Direction Set Register */ |
263 | #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC(n)) | 263 | #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC(n)) /* Direction Clear Register */ |
264 | #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG(n)) | 264 | #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG(n)) /* Trigger Register */ |
265 | #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS(n)) | 265 | #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS(n)) /* Trigger Set Register */ |
266 | #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC(n)) | 266 | #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC(n)) /* Trigger Clear Register */ |
267 | #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG(n)) | 267 | #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG(n)) /* Port Flag Register */ |
268 | #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC(n)) | 268 | #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC(n)) /* Port Flag clear Register */ |
269 | #define REG_GPIO_PXDS0(n) REG32(GPIO_PXDS0(n)) | 269 | #define REG_GPIO_PXDS0(n) REG32(GPIO_PXDS0(n)) /* Port Drive Strength*/ |
270 | #define REG_GPIO_PXDS0S(n) REG32(GPIO_PXDS0S(n)) | 270 | #define REG_GPIO_PXDS0S(n) REG32(GPIO_PXDS0S(n)) |
271 | #define REG_GPIO_PXDS0C(n) REG32(GPIO_PXDS0C(n)) | 271 | #define REG_GPIO_PXDS0C(n) REG32(GPIO_PXDS0C(n)) |
272 | #define REG_GPIO_PXDS1(n) REG32(GPIO_PXDS1(n)) | 272 | #define REG_GPIO_PXDS1(n) REG32(GPIO_PXDS1(n)) |
diff --git a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c index 89251b727d..ea29ce266d 100644 --- a/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c +++ b/firmware/target/mips/ingenic_jz47xx/xduoo_x3/lcd-xduoo_x3.c | |||
@@ -301,28 +301,29 @@ void lcd_blit_mono(const unsigned char *data, int x, int by, int width, | |||
301 | void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) ICODE_ATTR; | 301 | void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) ICODE_ATTR; |
302 | void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) | 302 | void lcd_grey_data(unsigned char *values, unsigned char *phases, int count) |
303 | { | 303 | { |
304 | unsigned char a, b, c, d; | 304 | unsigned long ltmp; |
305 | unsigned long *lval = (unsigned long *)values; | ||
306 | unsigned long *lpha = (unsigned long *)phases; | ||
307 | const unsigned long mask = 0x80808080; | ||
305 | 308 | ||
306 | __gpio_set_pin(PIN_LCD_DC); | ||
307 | while(count--) | 309 | while(count--) |
308 | { | 310 | { |
309 | c = 0; | 311 | /* calculate disp data from phase we only use the last byte (8bits) */ |
310 | d = 8; | 312 | ltmp = mask & lpha[0]; // ltmp= 3.......2.......1.......0....... |
311 | while(d--) | 313 | ltmp |= (mask & lpha[1]) >> 4; // ltmp= 7.......6.......5.......4....... |
312 | { | 314 | /* phase0 | phase1 >> 4 */ // ltmp= 3...7...2...6...1...5...0...4... |
313 | a = *phases; | 315 | ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..12..56..01..45.. |
314 | b = *values++; | 316 | ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..123.567.012.456. |
315 | b += a & ~0x80; | 317 | ltmp |= ltmp >> 9; // ltmp= 3...7...23..67..123.567.01234567 |
316 | *phases++ = b; | 318 | |
317 | c <<= 1; | 319 | /* update the phases */ |
318 | c |= a >> 7; | 320 | lpha[0] = lval[0] + (lpha[0] & ~mask); |
319 | } | 321 | lpha[1] = lval[1] + (lpha[1] & ~mask); |
320 | REG_GPIO_PXDATC(2) = 0x000030FC; | 322 | |
321 | REG_GPIO_PXDATS(2) = ((c & 0xC0) << 6) | ((c & 0x3F) << 2); | 323 | lcd_write_data((const fb_data*) <mp, 1); |
322 | __gpio_clear_pin(PIN_LCD_WR); | 324 | |
323 | bitdelay(); | 325 | lpha+=2; |
324 | __gpio_set_pin(PIN_LCD_WR); | 326 | lval+=2; |
325 | bitdelay(); | ||
326 | } | 327 | } |
327 | } | 328 | } |
328 | 329 | ||