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| author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-30 21:24:36 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-30 21:36:26 -0400 |
| commit | 8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb (patch) | |
| tree | 613042111cd214bb267a6d9cec0f81b0c0830ea9 /firmware/target/mips/ingenic_jz47xx/system-target.h | |
| parent | 06e9abc428fc5add36bebf9fed8a5a6353e41b21 (diff) | |
| download | rockbox-8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb.tar.gz rockbox-8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb.zip | |
jz4760: Explicitly disable UARTs at startup
(Bootloader uses UART1, and leaves it running when it hands it off to us)
Change-Id: Icde1d713574582f18e9f91b5c95f3917fe324b74
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-target.h')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-target.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h index dd42fac633..d8c395cef2 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-target.h +++ b/firmware/target/mips/ingenic_jz47xx/system-target.h | |||
| @@ -32,6 +32,8 @@ | |||
| 32 | #define CACHE_LINE_SIZE 32 | 32 | #define CACHE_LINE_SIZE 32 |
| 33 | #include "mmu-mips.h" | 33 | #include "mmu-mips.h" |
| 34 | 34 | ||
| 35 | #define CFG_UART_BASE UART1_BASE /* Base of the UART channel */ | ||
| 36 | |||
| 35 | /* no optimized byteswap functions implemented for mips, yet */ | 37 | /* no optimized byteswap functions implemented for mips, yet */ |
| 36 | #define NEED_GENERIC_BYTESWAPS | 38 | #define NEED_GENERIC_BYTESWAPS |
| 37 | 39 | ||