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author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-30 21:24:36 -0400 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-30 21:36:26 -0400 |
commit | 8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb (patch) | |
tree | 613042111cd214bb267a6d9cec0f81b0c0830ea9 | |
parent | 06e9abc428fc5add36bebf9fed8a5a6353e41b21 (diff) | |
download | rockbox-8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb.tar.gz rockbox-8dadce5c4cc9564cfeb49f42ec83fd1727c9ccdb.zip |
jz4760: Explicitly disable UARTs at startup
(Bootloader uses UART1, and leaves it running when it hands it off to us)
Change-Id: Icde1d713574582f18e9f91b5c95f3917fe324b74
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/debug-jz4760.c | 12 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 12 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-target.h | 2 |
3 files changed, 24 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c index ee247a9cff..3634a88f11 100644 --- a/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/debug-jz4760.c | |||
@@ -138,6 +138,8 @@ bool dbg_ports(void) | |||
138 | return false; | 138 | return false; |
139 | } | 139 | } |
140 | 140 | ||
141 | extern uint32_t irqstackend,irqstackbegin; | ||
142 | |||
141 | bool dbg_hw_info(void) | 143 | bool dbg_hw_info(void) |
142 | { | 144 | { |
143 | int btn = 0; | 145 | int btn = 0; |
@@ -151,6 +153,12 @@ bool dbg_hw_info(void) | |||
151 | { | 153 | { |
152 | lcd_clear_display(); | 154 | lcd_clear_display(); |
153 | line = 0; | 155 | line = 0; |
156 | |||
157 | uint32_t *ptr = &irqstackbegin; | ||
158 | for ( ; ptr < &irqstackend && *ptr == 0xDEADBEEF; ptr++) {} | ||
159 | |||
160 | lcd_putsf(0, line++, "IRQ stack max: %d", (uint32_t)&irqstackend - (uint32_t)ptr); | ||
161 | |||
154 | display_clocks(); | 162 | display_clocks(); |
155 | display_enabled_clocks(); | 163 | display_enabled_clocks(); |
156 | #ifdef HAVE_TOUCHSCREEN | 164 | #ifdef HAVE_TOUCHSCREEN |
@@ -169,8 +177,7 @@ bool dbg_hw_info(void) | |||
169 | return true; | 177 | return true; |
170 | } | 178 | } |
171 | 179 | ||
172 | #define CFG_UART_BASE UART1_BASE /* Base of the UART channel */ | 180 | #ifdef WITH_SERIAL |
173 | |||
174 | void serial_putc (const char c) | 181 | void serial_putc (const char c) |
175 | { | 182 | { |
176 | volatile u8 *uart_lsr = (volatile u8 *)(CFG_UART_BASE + OFF_LSR); | 183 | volatile u8 *uart_lsr = (volatile u8 *)(CFG_UART_BASE + OFF_LSR); |
@@ -271,3 +278,4 @@ void serial_dump_data(unsigned char* data, int len) | |||
271 | 278 | ||
272 | serial_putc( '\n' ); | 279 | serial_putc( '\n' ); |
273 | } | 280 | } |
281 | #endif | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index 4489212ccc..a8e40e4e31 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
@@ -29,6 +29,9 @@ | |||
29 | #include "power.h" | 29 | #include "power.h" |
30 | 30 | ||
31 | //#define USE_HW_UDELAY // This is BROKEN. | 31 | //#define USE_HW_UDELAY // This is BROKEN. |
32 | #ifdef BOOTLOADER | ||
33 | #define WITH_SERIAL | ||
34 | #endif | ||
32 | 35 | ||
33 | static int irq; | 36 | static int irq; |
34 | static void UIRQ(void) | 37 | static void UIRQ(void) |
@@ -535,6 +538,7 @@ void pll1_disable(void) | |||
535 | REG_CPM_CPPCR1 &= ~CPPCR1_PLL1EN; | 538 | REG_CPM_CPPCR1 &= ~CPPCR1_PLL1EN; |
536 | } | 539 | } |
537 | 540 | ||
541 | #ifdef WITH_SERIAL | ||
538 | static void serial_setbrg(void) | 542 | static void serial_setbrg(void) |
539 | { | 543 | { |
540 | volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR); | 544 | volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR); |
@@ -589,6 +593,7 @@ int serial_preinit(void) | |||
589 | 593 | ||
590 | return 0; | 594 | return 0; |
591 | } | 595 | } |
596 | #endif | ||
592 | 597 | ||
593 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | 598 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ |
594 | #define cpu_frequency CPU_FREQ | 599 | #define cpu_frequency CPU_FREQ |
@@ -698,7 +703,14 @@ void ICODE_ATTR system_main(void) | |||
698 | pll0_init(CPUFREQ_DEFAULT); // PLL0 drives everything but audio | 703 | pll0_init(CPUFREQ_DEFAULT); // PLL0 drives everything but audio |
699 | pll1_disable(); // Leave PLL1 disabled until audio needs it | 704 | pll1_disable(); // Leave PLL1 disabled until audio needs it |
700 | 705 | ||
706 | /* Make sure UARTs are off */ | ||
707 | __cpm_stop_uart0(); | ||
708 | __cpm_stop_uart1(); | ||
709 | __cpm_stop_uart2(); | ||
710 | #ifdef WITH_SERIAL | ||
701 | serial_preinit(); | 711 | serial_preinit(); |
712 | #endif | ||
713 | |||
702 | usb_preinit(); | 714 | usb_preinit(); |
703 | dma_preinit(); | 715 | dma_preinit(); |
704 | 716 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h index dd42fac633..d8c395cef2 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-target.h +++ b/firmware/target/mips/ingenic_jz47xx/system-target.h | |||
@@ -32,6 +32,8 @@ | |||
32 | #define CACHE_LINE_SIZE 32 | 32 | #define CACHE_LINE_SIZE 32 |
33 | #include "mmu-mips.h" | 33 | #include "mmu-mips.h" |
34 | 34 | ||
35 | #define CFG_UART_BASE UART1_BASE /* Base of the UART channel */ | ||
36 | |||
35 | /* no optimized byteswap functions implemented for mips, yet */ | 37 | /* no optimized byteswap functions implemented for mips, yet */ |
36 | #define NEED_GENERIC_BYTESWAPS | 38 | #define NEED_GENERIC_BYTESWAPS |
37 | 39 | ||