mips: Heavily rework DMA & caching code

Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.

Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70

1 files changed, 7 insertions, 8 deletions

diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
index 87094dd7ae..d3a753a58e 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c
@@ -511,24 +511,23 @@ static void sdram_init(void)
 void ICODE_ATTR system_main(void)
 {
     int i;
-       
-    __dcache_writeback_all();
-    __icache_invalidate_all();
-    
+
+    commit_discard_idcache();
+
     write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */
-    
+
     /* Disable all interrupts */
     for(i=0; i<IRQ_MAX; i++)
         dis_irq(i);
-    
+
     mmu_init();
     pll_init();
     sdram_init();
-    
+
     /* Disable unneeded clocks, clocks are enabled when needed */
     __cpm_stop_all();
     __cpm_suspend_usbhost();
-    
+
     /* Enable interrupts at core level */
     enable_interrupt();
 }