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authorWilliam Wilgus <wilgus.william@gmail.com>2020-08-29 10:14:03 -0400
committerWilliam Wilgus <wilgus.william@gmail.com>2020-08-29 10:14:03 -0400
commit3867f0b95958a6219ed5b459c22b246fb827efe2 (patch)
tree76d3677f5cd31108d0449603506569433543bbc7 /firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
parent6296b220e5408feda177346a5a439ce4c6803a83 (diff)
downloadrockbox-3867f0b95958a6219ed5b459c22b246fb827efe2.tar.gz
rockbox-3867f0b95958a6219ed5b459c22b246fb827efe2.zip
XduooX3 Sources WS changes
Change-Id: I17ae59e7ef0440756527ce50ab30f8bf34f79007
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
index c644b9f477..cf676622f1 100644
--- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
+++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c
@@ -53,7 +53,7 @@ void lcd_clock_disable(void)
53void lcd_init_device(void) 53void lcd_init_device(void)
54{ 54{
55 lcd_init_controller(); 55 lcd_init_controller();
56 56
57 lcd_is_on = true; 57 lcd_is_on = true;
58 mutex_init(&lcd_mtx); 58 mutex_init(&lcd_mtx);
59 semaphore_init(&lcd_wkup, 1, 0); 59 semaphore_init(&lcd_wkup, 1, 0);
@@ -93,41 +93,41 @@ void lcd_update_rect(int x, int y, int width, int height)
93 width = LCD_WIDTH; 93 width = LCD_WIDTH;
94 94
95 mutex_lock(&lcd_mtx); 95 mutex_lock(&lcd_mtx);
96 96
97 lcd_clock_enable(); 97 lcd_clock_enable();
98 98
99 lcd_set_target(x, y, width, height); 99 lcd_set_target(x, y, width, height);
100 100
101 dma_enable(); 101 dma_enable();
102 102
103 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; 103 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES;
104 REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)FBADDR(x,y)); 104 REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)FBADDR(x,y));
105 REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; 105 REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD;
106 REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO); 106 REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO);
107 REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3; 107 REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3;
108 108
109 REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 109 REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32
110 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE ); 110 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE );
111 111
112 __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size. 112 __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size.
113 We need to find a way to make the framebuffer uncached, so this statement can get removed. */ 113 We need to find a way to make the framebuffer uncached, so this statement can get removed. */
114 114
115 while(REG_SLCD_STATE & SLCD_STATE_BUSY); 115 while(REG_SLCD_STATE & SLCD_STATE_BUSY);
116 REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN; /* Enable SLCD DMA support */ 116 REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN; /* Enable SLCD DMA support */
117 117
118 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ 118 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
119 REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ 119 REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */
120 120
121 semaphore_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ 121 semaphore_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */
122 122
123 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ 123 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
124 dma_disable(); 124 dma_disable();
125 125
126 while(REG_SLCD_STATE & SLCD_STATE_BUSY); 126 while(REG_SLCD_STATE & SLCD_STATE_BUSY);
127 REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; /* Disable SLCD DMA support */ 127 REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; /* Disable SLCD DMA support */
128 128
129 lcd_clock_disable(); 129 lcd_clock_disable();
130 130
131 mutex_unlock(&lcd_mtx); 131 mutex_unlock(&lcd_mtx);
132} 132}
133 133
@@ -144,7 +144,7 @@ void DMA_CALLBACK(DMA_LCD_CHANNEL)(void)
144 144
145 if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) 145 if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT)
146 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT; 146 REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT;
147 147
148 semaphore_release(&lcd_wkup); 148 semaphore_release(&lcd_wkup);
149} 149}
150 150
@@ -154,7 +154,7 @@ void lcd_update(void)
154{ 154{
155 if(!lcd_is_on) 155 if(!lcd_is_on)
156 return; 156 return;
157 157
158 lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); 158 lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
159} 159}
160 160
@@ -165,55 +165,55 @@ void lcd_blit_yuv(unsigned char * const src[3],
165{ 165{
166 unsigned char const * yuv_src[3]; 166 unsigned char const * yuv_src[3];
167 register off_t z; 167 register off_t z;
168 168
169 if(!lcd_is_on) 169 if(!lcd_is_on)
170 return; 170 return;
171 171
172 z = stride * src_y; 172 z = stride * src_y;
173 yuv_src[0] = src[0] + z + src_x; 173 yuv_src[0] = src[0] + z + src_x;
174 yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1); 174 yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1);
175 yuv_src[2] = src[2] + (yuv_src[1] - src[1]); 175 yuv_src[2] = src[2] + (yuv_src[1] - src[1]);
176 176
177 __dcache_writeback_all(); 177 __dcache_writeback_all();
178 178
179 __cpm_start_ipu(); 179 __cpm_start_ipu();
180 180
181 IPU_STOP_IPU(); 181 IPU_STOP_IPU();
182 IPU_RESET_IPU(); 182 IPU_RESET_IPU();
183 IPU_CLEAR_END_FLAG(); 183 IPU_CLEAR_END_FLAG();
184 184
185 IPU_DISABLE_RSIZE(); 185 IPU_DISABLE_RSIZE();
186 IPU_DISABLE_IRQ(); 186 IPU_DISABLE_IRQ();
187 187
188 IPU_SET_INFMT(INFMT_YUV420); 188 IPU_SET_INFMT(INFMT_YUV420);
189 IPU_SET_OUTFMT(OUTFMT_RGB565); 189 IPU_SET_OUTFMT(OUTFMT_RGB565);
190 190
191 IPU_SET_IN_FM(width, height); 191 IPU_SET_IN_FM(width, height);
192 IPU_SET_Y_STRIDE(stride); 192 IPU_SET_Y_STRIDE(stride);
193 IPU_SET_UV_STRIDE(stride, stride); 193 IPU_SET_UV_STRIDE(stride, stride);
194 194
195 IPU_SET_Y_ADDR(PHYSADDR((unsigned long)yuv_src[0])); 195 IPU_SET_Y_ADDR(PHYSADDR((unsigned long)yuv_src[0]));
196 IPU_SET_U_ADDR(PHYSADDR((unsigned long)yuv_src[1])); 196 IPU_SET_U_ADDR(PHYSADDR((unsigned long)yuv_src[1]));
197 IPU_SET_V_ADDR(PHYSADDR((unsigned long)yuv_src[2])); 197 IPU_SET_V_ADDR(PHYSADDR((unsigned long)yuv_src[2]));
198 IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)FBADDR(y,x))); 198 IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)FBADDR(y,x)));
199 199
200 IPU_SET_OUT_FM(height, width); 200 IPU_SET_OUT_FM(height, width);
201 IPU_SET_OUT_STRIDE(height); 201 IPU_SET_OUT_STRIDE(height);
202 202
203 IPU_SET_CSC_C0_COEF(YUV_CSC_C0); 203 IPU_SET_CSC_C0_COEF(YUV_CSC_C0);
204 IPU_SET_CSC_C1_COEF(YUV_CSC_C1); 204 IPU_SET_CSC_C1_COEF(YUV_CSC_C1);
205 IPU_SET_CSC_C2_COEF(YUV_CSC_C2); 205 IPU_SET_CSC_C2_COEF(YUV_CSC_C2);
206 IPU_SET_CSC_C3_COEF(YUV_CSC_C3); 206 IPU_SET_CSC_C3_COEF(YUV_CSC_C3);
207 IPU_SET_CSC_C4_COEF(YUV_CSC_C4); 207 IPU_SET_CSC_C4_COEF(YUV_CSC_C4);
208 208
209 IPU_RUN_IPU(); 209 IPU_RUN_IPU();
210 210
211 while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED()); 211 while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED());
212 212
213 IPU_CLEAR_END_FLAG(); 213 IPU_CLEAR_END_FLAG();
214 IPU_STOP_IPU(); 214 IPU_STOP_IPU();
215 IPU_RESET_IPU(); 215 IPU_RESET_IPU();
216 216
217 __cpm_stop_ipu(); 217 __cpm_stop_ipu();
218 218
219 /* YUV speed is limited by LCD speed */ 219 /* YUV speed is limited by LCD speed */