From 3867f0b95958a6219ed5b459c22b246fb827efe2 Mon Sep 17 00:00:00 2001 From: William Wilgus Date: Sat, 29 Aug 2020 10:14:03 -0400 Subject: XduooX3 Sources WS changes Change-Id: I17ae59e7ef0440756527ce50ab30f8bf34f79007 --- firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c | 60 ++++++++++++------------ 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c') diff --git a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c index c644b9f477..cf676622f1 100644 --- a/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/lcd-jz4740.c @@ -53,7 +53,7 @@ void lcd_clock_disable(void) void lcd_init_device(void) { lcd_init_controller(); - + lcd_is_on = true; mutex_init(&lcd_mtx); semaphore_init(&lcd_wkup, 1, 0); @@ -93,41 +93,41 @@ void lcd_update_rect(int x, int y, int width, int height) width = LCD_WIDTH; mutex_lock(&lcd_mtx); - + lcd_clock_enable(); - + lcd_set_target(x, y, width, height); - + dma_enable(); - + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) = DMAC_DCCSR_NDES; REG_DMAC_DSAR(DMA_LCD_CHANNEL) = PHYSADDR((unsigned long)FBADDR(x,y)); REG_DMAC_DRSR(DMA_LCD_CHANNEL) = DMAC_DRSR_RS_SLCD; REG_DMAC_DTAR(DMA_LCD_CHANNEL) = PHYSADDR(SLCD_FIFO); REG_DMAC_DTCR(DMA_LCD_CHANNEL) = (width * height) >> 3; - + REG_DMAC_DCMD(DMA_LCD_CHANNEL) = ( DMAC_DCMD_SAI | DMAC_DCMD_RDIL_IGN | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_16BYTE ); - + __dcache_writeback_all(); /* Size of framebuffer is way bigger than cache size. We need to find a way to make the framebuffer uncached, so this statement can get removed. */ - + while(REG_SLCD_STATE & SLCD_STATE_BUSY); REG_SLCD_CTRL |= SLCD_CTRL_DMA_EN; /* Enable SLCD DMA support */ - + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */ REG_DMAC_DCMD(DMA_LCD_CHANNEL) |= DMAC_DCMD_TIE; /* Enable DMA interrupt */ semaphore_wait(&lcd_wkup, TIMEOUT_BLOCK); /* Sleeping in lcd_update() should be safe */ - + REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */ dma_disable(); - + while(REG_SLCD_STATE & SLCD_STATE_BUSY); REG_SLCD_CTRL &= ~SLCD_CTRL_DMA_EN; /* Disable SLCD DMA support */ - + lcd_clock_disable(); - + mutex_unlock(&lcd_mtx); } @@ -144,7 +144,7 @@ void DMA_CALLBACK(DMA_LCD_CHANNEL)(void) if (REG_DMAC_DCCSR(DMA_LCD_CHANNEL) & DMAC_DCCSR_TT) REG_DMAC_DCCSR(DMA_LCD_CHANNEL) &= ~DMAC_DCCSR_TT; - + semaphore_release(&lcd_wkup); } @@ -154,7 +154,7 @@ void lcd_update(void) { if(!lcd_is_on) return; - + lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT); } @@ -165,55 +165,55 @@ void lcd_blit_yuv(unsigned char * const src[3], { unsigned char const * yuv_src[3]; register off_t z; - + if(!lcd_is_on) return; - + z = stride * src_y; yuv_src[0] = src[0] + z + src_x; yuv_src[1] = src[1] + (z >> 2) + (src_x >> 1); yuv_src[2] = src[2] + (yuv_src[1] - src[1]); - + __dcache_writeback_all(); - + __cpm_start_ipu(); - + IPU_STOP_IPU(); IPU_RESET_IPU(); IPU_CLEAR_END_FLAG(); - + IPU_DISABLE_RSIZE(); IPU_DISABLE_IRQ(); - + IPU_SET_INFMT(INFMT_YUV420); IPU_SET_OUTFMT(OUTFMT_RGB565); - + IPU_SET_IN_FM(width, height); IPU_SET_Y_STRIDE(stride); IPU_SET_UV_STRIDE(stride, stride); - + IPU_SET_Y_ADDR(PHYSADDR((unsigned long)yuv_src[0])); IPU_SET_U_ADDR(PHYSADDR((unsigned long)yuv_src[1])); IPU_SET_V_ADDR(PHYSADDR((unsigned long)yuv_src[2])); IPU_SET_OUT_ADDR(PHYSADDR((unsigned long)FBADDR(y,x))); - + IPU_SET_OUT_FM(height, width); IPU_SET_OUT_STRIDE(height); - + IPU_SET_CSC_C0_COEF(YUV_CSC_C0); IPU_SET_CSC_C1_COEF(YUV_CSC_C1); IPU_SET_CSC_C2_COEF(YUV_CSC_C2); IPU_SET_CSC_C3_COEF(YUV_CSC_C3); IPU_SET_CSC_C4_COEF(YUV_CSC_C4); - + IPU_RUN_IPU(); - + while(!(IPU_POLLING_END_FLAG()) && IPU_IS_ENABLED()); - + IPU_CLEAR_END_FLAG(); IPU_STOP_IPU(); IPU_RESET_IPU(); - + __cpm_stop_ipu(); /* YUV speed is limited by LCD speed */ -- cgit v1.2.3