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author | Solomon Peachy <pizza@shaftnet.org> | 2018-06-28 06:24:26 -0400 |
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committer | Michael Giacomelli <giac2000@hotmail.com> | 2018-07-28 10:56:31 -0400 |
commit | 0662793ca0050e823cd1207cc4689a1cba5068bd (patch) | |
tree | 08cd2ec59c9044c96b697b5bf8d0640841d044e0 /firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c | |
parent | b3e2bd619b1b7ea94ef29d32db48e80b347a1990 (diff) | |
download | rockbox-0662793ca0050e823cd1207cc4689a1cba5068bd.tar.gz rockbox-0662793ca0050e823cd1207cc4689a1cba5068bd.zip |
Add cleaned-up xDuoo X3 support
Cleaned up, rebased, and forward-ported from the xvortex fork.
(original credit to vsoftster@gmail.com)
Change-Id: Ibcc023a0271ea81e901450a88317708c2683236d
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c b/firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c new file mode 100644 index 0000000000..ab0f152669 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/kernel-jz4760.c | |||
@@ -0,0 +1,53 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2016 by Roman Stolyarov | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "system.h" | ||
24 | #include "kernel.h" | ||
25 | #include "cpu.h" | ||
26 | |||
27 | void tick_start(unsigned int interval_in_ms) | ||
28 | { | ||
29 | unsigned int latch; | ||
30 | |||
31 | /* 12Mhz / 4 = 3Mhz */ | ||
32 | latch = interval_in_ms*1000 * 3; | ||
33 | |||
34 | REG_OST_OSTCSR = OSTCSR_PRESCALE4 | OSTCSR_EXT_EN; | ||
35 | REG_OST_OSTDR = latch; | ||
36 | REG_OST_OSTCNTL = 0; | ||
37 | REG_OST_OSTCNTH = 0; | ||
38 | |||
39 | system_enable_irq(IRQ_TCU0); | ||
40 | |||
41 | REG_TCU_TMCR = TMCR_OSTMASK; /* unmask match irq */ | ||
42 | REG_TCU_TSCR = TSCR_OST; /* enable timer clock */ | ||
43 | REG_TCU_TESR = TESR_OST; /* start counting up */ | ||
44 | } | ||
45 | |||
46 | /* Interrupt handler */ | ||
47 | void TCU0(void) | ||
48 | { | ||
49 | REG_TCU_TFCR = TFCR_OSTFLAG; /* ACK timer */ | ||
50 | |||
51 | /* Run through the list of tick tasks */ | ||
52 | call_tick_tasks(); | ||
53 | } | ||