summaryrefslogtreecommitdiff
path: root/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
diff options
context:
space:
mode:
authorSolomon Peachy <pizza@shaftnet.org>2020-08-28 21:45:58 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-09-03 15:34:28 -0400
commit0cb162a76b16d58250a33e817af6a763e89a770a (patch)
treeaf5ac50c1ec59f665e0a4845672a16d758b44953 /firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
parent1ae8213a64c23ac86173b8139e01c7cad350ec6b (diff)
downloadrockbox-0cb162a76b16d58250a33e817af6a763e89a770a.tar.gz
rockbox-0cb162a76b16d58250a33e817af6a763e89a770a.zip
mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527) but rebased and heavily updated. Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c b/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
index 4cdea2ad08..87d2b4e210 100644
--- a/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/dma_acc-jz4760.c
@@ -29,7 +29,7 @@ void memset_dma(void *target, int c, size_t len, unsigned int bits)
29 unsigned char *dp; 29 unsigned char *dp;
30 30
31 if(((unsigned int)target < 0xa0000000) && len) 31 if(((unsigned int)target < 0xa0000000) && len)
32 dma_cache_wback_inv((unsigned long)target, len); 32 discard_dcache_range(target, len);
33 33
34 dp = (unsigned char *)((unsigned int)(&d) | 0xa0000000); 34 dp = (unsigned char *)((unsigned int)(&d) | 0xa0000000);
35 *(dp + 0) = c; 35 *(dp + 0) = c;
@@ -68,14 +68,14 @@ void memset_dma(void *target, int c, size_t len, unsigned int bits)
68void memcpy_dma(void *target, const void *source, size_t len, unsigned int bits) 68void memcpy_dma(void *target, const void *source, size_t len, unsigned int bits)
69{ 69{
70 if(((unsigned int)source < 0xa0000000) && len) 70 if(((unsigned int)source < 0xa0000000) && len)
71 dma_cache_wback_inv((unsigned long)source, len); 71 commit_dcache_range(source, len);
72 72
73 if(((unsigned int)target < 0xa0000000) && len) 73 if(((unsigned int)target < 0xa0000000) && len)
74 dma_cache_wback_inv((unsigned long)target, len); 74 discard_dcache_range(target, len);
75 75
76 REG_MDMAC_DCCSR(MDMA_CHANNEL) = 0; 76 REG_MDMAC_DCCSR(MDMA_CHANNEL) = 0;
77 REG_MDMAC_DSAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)source); 77 REG_MDMAC_DSAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)source);
78 REG_MDMAC_DTAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)target); 78 REG_MDMAC_DTAR(MDMA_CHANNEL) = PHYSADDR((unsigned long)target);
79 REG_MDMAC_DRSR(MDMA_CHANNEL) = DMAC_DRSR_RS_AUTO; 79 REG_MDMAC_DRSR(MDMA_CHANNEL) = DMAC_DRSR_RS_AUTO;
80 switch (bits) 80 switch (bits)
81 { 81 {