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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2008-07-14 15:03:10 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2008-07-14 15:03:10 +0000
commit0709f0a5c60b5525ff98708887f5f1e5b0b570c2 (patch)
tree849fd125aa7b217228d584212d2930d8259ff5d8 /firmware/target/mips/ingenic_jz47xx/boot.lds
parent4f199817488708ba60724accb6ce76886f855af8 (diff)
downloadrockbox-0709f0a5c60b5525ff98708887f5f1e5b0b570c2.tar.gz
rockbox-0709f0a5c60b5525ff98708887f5f1e5b0b570c2.zip
Add preliminary support for the Onda VX747 (MIPS target)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@18032 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/boot.lds')
-rwxr-xr-xfirmware/target/mips/ingenic_jz47xx/boot.lds107
1 files changed, 107 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/boot.lds b/firmware/target/mips/ingenic_jz47xx/boot.lds
new file mode 100755
index 0000000000..9bc635afad
--- /dev/null
+++ b/firmware/target/mips/ingenic_jz47xx/boot.lds
@@ -0,0 +1,107 @@
1#include "config.h"
2#undef mips
3
4OUTPUT_FORMAT("elf32-tradlittlemips")
5OUTPUT_ARCH(MIPS)
6ENTRY(_start)
7STARTUP(target/mips/ingenic_jz47xx/crt0.o)
8
9#define DRAMSIZE (MEMORYSIZE * 0x100000)
10
11#define DRAMORIG 0x80E00000 /* HACK */
12#define IRAMORIG 0x80000000
13#define IRAMSIZE 16K
14
15MEMORY
16{
17 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
18 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
19}
20
21SECTIONS
22{
23 . = DRAMORIG;
24
25 .text : {
26 loadaddress = .;
27 _loadaddress = .;
28 *(.init.text);
29 *(.text*);
30 *(.glue_7);
31 *(.glue_7t);
32 . = ALIGN(0x4);
33 } > DRAM
34
35 . = ALIGN(4);
36
37 .rodata :
38 {
39 *(.rodata); /* problems without this, dunno why */
40 *(.rodata*);
41 *(.rodata.str1.1);
42 *(.rodata.str1.4);
43 . = ALIGN(0x4);
44
45 /* Pseudo-allocate the copies of the data sections */
46 _datacopy = .;
47 } > DRAM
48
49 . = ALIGN(4);
50
51 .data : {
52 *(.icode);
53 *(.irodata);
54 *(.idata);
55 *(.data*);
56 *(.scommon*);
57 *(.sdata*);
58 . = ALIGN(0x4);
59 _dataend = . ;
60 } > DRAM
61
62 . = ALIGN(4);
63
64 _gp = ALIGN(16);
65 .got : {
66 *(.got*)
67 }> DRAM
68
69 . = ALIGN(4);
70
71 .stack :
72 {
73 *(.stack)
74 _stackbegin = .;
75 stackbegin = .;
76 . += 0x2000;
77 _stackend = .;
78 stackend = .;
79 } > DRAM
80
81 . = ALIGN(4);
82
83 .bss :
84 {
85 _edata = .;
86 *(.sbss*);
87 *(.bss*);
88 *(.ibss);
89 *(COMMON)
90 _end = .;
91 } > DRAM
92
93 . = ALIGN(4);
94
95 .vectors IRAMORIG :
96 {
97 _vectorsstart = .;
98 KEEP(*(.resetvectors));
99 *(.resetvectors);
100 KEEP(*(.vectors));
101 *(.vectors);
102 _vectorsend = .;
103 } AT > DRAM
104 _vectorscopy = LOADADDR(.vectors);
105
106 . = ALIGN(4);
107}