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author | Solomon Peachy <pizza@shaftnet.org> | 2018-06-28 06:24:26 -0400 |
---|---|---|
committer | Michael Giacomelli <giac2000@hotmail.com> | 2018-07-28 10:56:31 -0400 |
commit | 0662793ca0050e823cd1207cc4689a1cba5068bd (patch) | |
tree | 08cd2ec59c9044c96b697b5bf8d0640841d044e0 /firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |
parent | b3e2bd619b1b7ea94ef29d32db48e80b347a1990 (diff) | |
download | rockbox-0662793ca0050e823cd1207cc4689a1cba5068bd.tar.gz rockbox-0662793ca0050e823cd1207cc4689a1cba5068bd.zip |
Add cleaned-up xDuoo X3 support
Cleaned up, rebased, and forward-ported from the xvortex fork.
(original credit to vsoftster@gmail.com)
Change-Id: Ibcc023a0271ea81e901450a88317708c2683236d
Signed-off-by: Solomon Peachy <pizza@shaftnet.org>
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | 1487 |
1 files changed, 1487 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c new file mode 100644 index 0000000000..c34f74a202 --- /dev/null +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |||
@@ -0,0 +1,1487 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2016 by Roman Stolyarov | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "gcc_extensions.h" | ||
24 | #include "cpu.h" | ||
25 | #include "ata-sd-target.h" | ||
26 | #include "dma-target.h" | ||
27 | #include "led.h" | ||
28 | #include "sdmmc.h" | ||
29 | #include "logf.h" | ||
30 | #include "storage.h" | ||
31 | #include "string.h" | ||
32 | |||
33 | static long last_disk_activity = -1; | ||
34 | static tCardInfo card[NUM_DRIVES]; | ||
35 | |||
36 | static struct mutex sd_mtx; | ||
37 | static struct semaphore sd_wakeup; | ||
38 | |||
39 | static int use_4bit[NUM_DRIVES]; | ||
40 | static int num_6[NUM_DRIVES]; | ||
41 | static int sd2_0[NUM_DRIVES]; | ||
42 | |||
43 | #define SD_DMA_ENABLE 1 | ||
44 | |||
45 | //#define DEBUG(x...) logf(x) | ||
46 | #define DEBUG(x, ...) | ||
47 | |||
48 | /* volumes */ | ||
49 | #define SD_SLOT_1 0 /* SD card 1 */ | ||
50 | #define SD_SLOT_2 1 /* SD card 2 */ | ||
51 | |||
52 | #define MSC_CHN(n) (2-n) | ||
53 | |||
54 | #define SD_IRQ_MASK(n) \ | ||
55 | do { \ | ||
56 | REG_MSC_IMASK(n) = 0xffff; \ | ||
57 | REG_MSC_IREG(n) = 0xffff; \ | ||
58 | } while (0) | ||
59 | |||
60 | /* Error codes */ | ||
61 | enum sd_result_t | ||
62 | { | ||
63 | SD_NO_RESPONSE = -1, | ||
64 | SD_NO_ERROR = 0, | ||
65 | SD_ERROR_OUT_OF_RANGE, | ||
66 | SD_ERROR_ADDRESS, | ||
67 | SD_ERROR_BLOCK_LEN, | ||
68 | SD_ERROR_ERASE_SEQ, | ||
69 | SD_ERROR_ERASE_PARAM, | ||
70 | SD_ERROR_WP_VIOLATION, | ||
71 | SD_ERROR_CARD_IS_LOCKED, | ||
72 | SD_ERROR_LOCK_UNLOCK_FAILED, | ||
73 | SD_ERROR_COM_CRC, | ||
74 | SD_ERROR_ILLEGAL_COMMAND, | ||
75 | SD_ERROR_CARD_ECC_FAILED, | ||
76 | SD_ERROR_CC, | ||
77 | SD_ERROR_GENERAL, | ||
78 | SD_ERROR_UNDERRUN, | ||
79 | SD_ERROR_OVERRUN, | ||
80 | SD_ERROR_CID_CSD_OVERWRITE, | ||
81 | SD_ERROR_STATE_MISMATCH, | ||
82 | SD_ERROR_HEADER_MISMATCH, | ||
83 | SD_ERROR_TIMEOUT, | ||
84 | SD_ERROR_CRC, | ||
85 | SD_ERROR_DRIVER_FAILURE, | ||
86 | }; | ||
87 | |||
88 | /* Standard MMC/SD clock speeds */ | ||
89 | #define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */ | ||
90 | #define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */ | ||
91 | #define SD_CLOCK_HIGH 48000000 /* 48 MHz for SD Cards */ | ||
92 | |||
93 | /* Extra commands for state control */ | ||
94 | /* Use negative numbers to disambiguate */ | ||
95 | #define SD_CIM_RESET -1 | ||
96 | |||
97 | /* Proprietary commands, illegal/reserved according to SD Specification 2.00 */ | ||
98 | /* class 1 */ | ||
99 | #define SD_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ | ||
100 | |||
101 | /* class 3 */ | ||
102 | #define SD_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ | ||
103 | |||
104 | /* class 4 */ | ||
105 | #define SD_PROGRAM_CID 26 /* adtc R1 */ | ||
106 | #define SD_PROGRAM_CSD 27 /* adtc R1 */ | ||
107 | |||
108 | /* class 9 */ | ||
109 | #define SD_GO_IRQ_STATE 40 /* bcr R5 */ | ||
110 | |||
111 | /* Don't change the order of these; they are used in dispatch tables */ | ||
112 | enum sd_rsp_t | ||
113 | { | ||
114 | RESPONSE_NONE = 0, | ||
115 | RESPONSE_R1 = 1, | ||
116 | RESPONSE_R1B = 2, | ||
117 | RESPONSE_R2_CID = 3, | ||
118 | RESPONSE_R2_CSD = 4, | ||
119 | RESPONSE_R3 = 5, | ||
120 | RESPONSE_R4 = 6, | ||
121 | RESPONSE_R5 = 7, | ||
122 | RESPONSE_R6 = 8, | ||
123 | RESPONSE_R7 = 9, | ||
124 | }; | ||
125 | |||
126 | /* | ||
127 | MMC status in R1 | ||
128 | Type | ||
129 | e : error bit | ||
130 | s : status bit | ||
131 | r : detected and set for the actual command response | ||
132 | x : detected and set during command execution. the host must poll | ||
133 | the card by sending status command in order to read these bits. | ||
134 | Clear condition | ||
135 | a : according to the card state | ||
136 | b : always related to the previous command. Reception of | ||
137 | a valid command will clear it (with a delay of one command) | ||
138 | c : clear by read | ||
139 | */ | ||
140 | |||
141 | #define R1_OUT_OF_RANGE (1 << 31) /* er, c */ | ||
142 | #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ | ||
143 | #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ | ||
144 | #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ | ||
145 | #define R1_ERASE_PARAM (1 << 27) /* ex, c */ | ||
146 | #define R1_WP_VIOLATION (1 << 26) /* erx, c */ | ||
147 | #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ | ||
148 | #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ | ||
149 | #define R1_COM_CRC_ERROR (1 << 23) /* er, b */ | ||
150 | #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ | ||
151 | #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ | ||
152 | #define R1_CC_ERROR (1 << 20) /* erx, c */ | ||
153 | #define R1_ERROR (1 << 19) /* erx, c */ | ||
154 | #define R1_UNDERRUN (1 << 18) /* ex, c */ | ||
155 | #define R1_OVERRUN (1 << 17) /* ex, c */ | ||
156 | #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ | ||
157 | #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ | ||
158 | #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ | ||
159 | #define R1_ERASE_RESET (1 << 13) /* sr, c */ | ||
160 | #define R1_STATUS(x) (x & 0xFFFFE000) | ||
161 | #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ | ||
162 | #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ | ||
163 | #define R1_APP_CMD (1 << 7) /* sr, c */ | ||
164 | |||
165 | /* These are unpacked versions of the actual responses */ | ||
166 | struct sd_response_r1 | ||
167 | { | ||
168 | unsigned char cmd; | ||
169 | unsigned int status; | ||
170 | }; | ||
171 | |||
172 | struct sd_response_r3 | ||
173 | { | ||
174 | unsigned int ocr; | ||
175 | }; | ||
176 | |||
177 | #define SD_CARD_BUSY 0x80000000 /* Card Power up status bit */ | ||
178 | |||
179 | struct sd_request | ||
180 | { | ||
181 | int index; /* Slot index - used for CS lines */ | ||
182 | int cmd; /* Command to send */ | ||
183 | unsigned int arg; /* Argument to send */ | ||
184 | enum sd_rsp_t rtype; /* Response type expected */ | ||
185 | |||
186 | /* Data transfer (these may be modified at the low level) */ | ||
187 | unsigned short nob; /* Number of blocks to transfer*/ | ||
188 | unsigned short block_len; /* Block length */ | ||
189 | unsigned char *buffer; /* Data buffer */ | ||
190 | unsigned int cnt; /* Data length, for PIO */ | ||
191 | |||
192 | /* Results */ | ||
193 | unsigned char response[18]; /* Buffer to store response - CRC is optional */ | ||
194 | enum sd_result_t result; | ||
195 | }; | ||
196 | |||
197 | #define SD_OCR_ARG 0x00ff8000 /* Argument of OCR */ | ||
198 | |||
199 | /*********************************************************************** | ||
200 | * SD Events | ||
201 | */ | ||
202 | #define SD_EVENT_NONE 0x00 /* No events */ | ||
203 | #define SD_EVENT_RX_DATA_DONE 0x01 /* Rx data done */ | ||
204 | #define SD_EVENT_TX_DATA_DONE 0x02 /* Tx data done */ | ||
205 | #define SD_EVENT_PROG_DONE 0x04 /* Programming is done */ | ||
206 | |||
207 | /************************************************************************** | ||
208 | * Utility functions | ||
209 | **************************************************************************/ | ||
210 | |||
211 | #define PARSE_U32(_buf,_index) \ | ||
212 | (((unsigned int)_buf[_index]) << 24) | (((unsigned int)_buf[_index+1]) << 16) | \ | ||
213 | (((unsigned int)_buf[_index+2]) << 8) | ((unsigned int)_buf[_index+3]); | ||
214 | |||
215 | #define PARSE_U16(_buf,_index) \ | ||
216 | (((unsigned short)_buf[_index]) << 8) | ((unsigned short)_buf[_index+1]); | ||
217 | |||
218 | static int sd_unpack_r1(struct sd_request *request, struct sd_response_r1 *r1) | ||
219 | { | ||
220 | unsigned char *buf = request->response; | ||
221 | |||
222 | if (request->result) | ||
223 | return request->result; | ||
224 | |||
225 | r1->cmd = buf[0]; | ||
226 | r1->status = PARSE_U32(buf,1); | ||
227 | |||
228 | DEBUG("sd_unpack_r1: cmd=%d status=%08x", r1->cmd, r1->status); | ||
229 | |||
230 | if (R1_STATUS(r1->status)) { | ||
231 | if (r1->status & R1_OUT_OF_RANGE) return SD_ERROR_OUT_OF_RANGE; | ||
232 | if (r1->status & R1_ADDRESS_ERROR) return SD_ERROR_ADDRESS; | ||
233 | if (r1->status & R1_BLOCK_LEN_ERROR) return SD_ERROR_BLOCK_LEN; | ||
234 | if (r1->status & R1_ERASE_SEQ_ERROR) return SD_ERROR_ERASE_SEQ; | ||
235 | if (r1->status & R1_ERASE_PARAM) return SD_ERROR_ERASE_PARAM; | ||
236 | if (r1->status & R1_WP_VIOLATION) return SD_ERROR_WP_VIOLATION; | ||
237 | //if (r1->status & R1_CARD_IS_LOCKED) return SD_ERROR_CARD_IS_LOCKED; | ||
238 | if (r1->status & R1_LOCK_UNLOCK_FAILED) return SD_ERROR_LOCK_UNLOCK_FAILED; | ||
239 | if (r1->status & R1_COM_CRC_ERROR) return SD_ERROR_COM_CRC; | ||
240 | if (r1->status & R1_ILLEGAL_COMMAND) return SD_ERROR_ILLEGAL_COMMAND; | ||
241 | if (r1->status & R1_CARD_ECC_FAILED) return SD_ERROR_CARD_ECC_FAILED; | ||
242 | if (r1->status & R1_CC_ERROR) return SD_ERROR_CC; | ||
243 | if (r1->status & R1_ERROR) return SD_ERROR_GENERAL; | ||
244 | if (r1->status & R1_UNDERRUN) return SD_ERROR_UNDERRUN; | ||
245 | if (r1->status & R1_OVERRUN) return SD_ERROR_OVERRUN; | ||
246 | if (r1->status & R1_CID_CSD_OVERWRITE) return SD_ERROR_CID_CSD_OVERWRITE; | ||
247 | } | ||
248 | |||
249 | if (buf[0] != request->cmd) | ||
250 | return SD_ERROR_HEADER_MISMATCH; | ||
251 | |||
252 | /* This should be last - it's the least dangerous error */ | ||
253 | |||
254 | return 0; | ||
255 | } | ||
256 | |||
257 | static int sd_unpack_r6(struct sd_request *request, struct sd_response_r1 *r1, unsigned long *rca) | ||
258 | { | ||
259 | unsigned char *buf = request->response; | ||
260 | |||
261 | if (request->result) | ||
262 | return request->result; | ||
263 | |||
264 | *rca = PARSE_U16(buf,1); /* Save RCA returned by the SD Card */ | ||
265 | |||
266 | *(buf+1) = 0; | ||
267 | *(buf+2) = 0; | ||
268 | |||
269 | return sd_unpack_r1(request, r1); | ||
270 | } | ||
271 | |||
272 | static int sd_unpack_r3(struct sd_request *request, struct sd_response_r3 *r3) | ||
273 | { | ||
274 | unsigned char *buf = request->response; | ||
275 | |||
276 | if (request->result) return request->result; | ||
277 | |||
278 | r3->ocr = PARSE_U32(buf,1); | ||
279 | DEBUG("sd_unpack_r3: ocr=%08x", r3->ocr); | ||
280 | |||
281 | if (buf[0] != 0x3f) | ||
282 | return SD_ERROR_HEADER_MISMATCH; | ||
283 | |||
284 | return 0; | ||
285 | } | ||
286 | |||
287 | /* Stop the MMC clock and wait while it happens */ | ||
288 | static inline int jz_sd_stop_clock(const int drive) | ||
289 | { | ||
290 | register int timeout = 1000; | ||
291 | |||
292 | //DEBUG("stop MMC clock"); | ||
293 | REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_STOP; | ||
294 | |||
295 | while (timeout && (REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_CLK_EN)) | ||
296 | { | ||
297 | timeout--; | ||
298 | if (timeout == 0) | ||
299 | { | ||
300 | DEBUG("Timeout on stop clock waiting"); | ||
301 | return SD_ERROR_TIMEOUT; | ||
302 | } | ||
303 | udelay(1); | ||
304 | } | ||
305 | //DEBUG("clock off time is %d microsec", timeout); | ||
306 | return SD_NO_ERROR; | ||
307 | } | ||
308 | |||
309 | /* Start the MMC clock and operation */ | ||
310 | static inline int jz_sd_start_clock(const int drive) | ||
311 | { | ||
312 | REG_MSC_STRPCL(MSC_CHN(drive)) = MSC_STRPCL_CLOCK_CONTROL_START | MSC_STRPCL_START_OP; | ||
313 | return SD_NO_ERROR; | ||
314 | } | ||
315 | |||
316 | static int jz_sd_check_status(const int drive, struct sd_request *request) | ||
317 | { | ||
318 | (void)request; | ||
319 | unsigned int status = REG_MSC_STAT(MSC_CHN(drive)); | ||
320 | |||
321 | /* Checking for response or data timeout */ | ||
322 | if (status & (MSC_STAT_TIME_OUT_RES | MSC_STAT_TIME_OUT_READ)) | ||
323 | { | ||
324 | DEBUG("SD timeout, MSC_STAT 0x%x CMD %d", status, | ||
325 | request->cmd); | ||
326 | return SD_ERROR_TIMEOUT; | ||
327 | } | ||
328 | |||
329 | /* Checking for CRC error */ | ||
330 | if (status & | ||
331 | (MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR | | ||
332 | MSC_STAT_CRC_RES_ERR)) | ||
333 | { | ||
334 | DEBUG("SD CRC error, MSC_STAT 0x%x", status); | ||
335 | return SD_ERROR_CRC; | ||
336 | |||
337 | } | ||
338 | |||
339 | |||
340 | /* Checking for FIFO empty */ | ||
341 | /*if(status & MSC_STAT_DATA_FIFO_EMPTY && request->rtype != RESPONSE_NONE) | ||
342 | { | ||
343 | DEBUG("SD FIFO empty, MSC_STAT 0x%x", status); | ||
344 | return SD_ERROR_UNDERRUN; | ||
345 | }*/ | ||
346 | |||
347 | return SD_NO_ERROR; | ||
348 | } | ||
349 | |||
350 | /* Obtain response to the command and store it to response buffer */ | ||
351 | static void jz_sd_get_response(const int drive, struct sd_request *request) | ||
352 | { | ||
353 | int i; | ||
354 | unsigned char *buf; | ||
355 | unsigned int data; | ||
356 | |||
357 | DEBUG("fetch response for request %d, cmd %d", request->rtype, | ||
358 | request->cmd); | ||
359 | buf = request->response; | ||
360 | request->result = SD_NO_ERROR; | ||
361 | |||
362 | switch (request->rtype) | ||
363 | { | ||
364 | case RESPONSE_R1: | ||
365 | case RESPONSE_R1B: | ||
366 | case RESPONSE_R7: | ||
367 | case RESPONSE_R6: | ||
368 | case RESPONSE_R3: | ||
369 | case RESPONSE_R4: | ||
370 | case RESPONSE_R5: | ||
371 | { | ||
372 | data = REG_MSC_RES(MSC_CHN(drive)); | ||
373 | buf[0] = (data >> 8) & 0xff; | ||
374 | buf[1] = data & 0xff; | ||
375 | data = REG_MSC_RES(MSC_CHN(drive)); | ||
376 | buf[2] = (data >> 8) & 0xff; | ||
377 | buf[3] = data & 0xff; | ||
378 | data = REG_MSC_RES(MSC_CHN(drive)); | ||
379 | buf[4] = data & 0xff; | ||
380 | |||
381 | DEBUG("request %d, response [%02x %02x %02x %02x %02x]", | ||
382 | request->rtype, buf[0], buf[1], buf[2], | ||
383 | buf[3], buf[4]); | ||
384 | break; | ||
385 | } | ||
386 | case RESPONSE_R2_CID: | ||
387 | case RESPONSE_R2_CSD: | ||
388 | { | ||
389 | for (i = 0; i < 16; i += 2) | ||
390 | { | ||
391 | data = REG_MSC_RES(MSC_CHN(drive)); | ||
392 | buf[i] = (data >> 8) & 0xff; | ||
393 | buf[i + 1] = data & 0xff; | ||
394 | } | ||
395 | DEBUG("request %d, response []", request->rtype); | ||
396 | break; | ||
397 | } | ||
398 | case RESPONSE_NONE: | ||
399 | DEBUG("No response"); | ||
400 | break; | ||
401 | |||
402 | default: | ||
403 | DEBUG("unhandled response type for request %d", | ||
404 | request->rtype); | ||
405 | break; | ||
406 | } | ||
407 | } | ||
408 | |||
409 | static int jz_sd_receive_data(const int drive, struct sd_request *req) | ||
410 | { | ||
411 | unsigned int nob = req->nob; | ||
412 | unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2; /* length in word */ | ||
413 | unsigned char *buf = req->buffer; | ||
414 | unsigned int *wbuf = (unsigned int *) buf; | ||
415 | unsigned int waligned = (((unsigned int) buf & 0x3) == 0); /* word aligned ? */ | ||
416 | unsigned int stat, timeout, data, cnt; | ||
417 | |||
418 | for (; nob >= 1; nob--) | ||
419 | { | ||
420 | timeout = 0x3FFFFFF; | ||
421 | |||
422 | while (timeout) | ||
423 | { | ||
424 | timeout--; | ||
425 | stat = REG_MSC_STAT(MSC_CHN(drive)); | ||
426 | |||
427 | if (stat & MSC_STAT_TIME_OUT_READ) | ||
428 | return SD_ERROR_TIMEOUT; | ||
429 | else if (stat & MSC_STAT_CRC_READ_ERROR) | ||
430 | return SD_ERROR_CRC; | ||
431 | else if (!(stat & MSC_STAT_DATA_FIFO_EMPTY) | ||
432 | || (stat & MSC_STAT_DATA_FIFO_AFULL)) | ||
433 | /* Ready to read data */ | ||
434 | break; | ||
435 | |||
436 | udelay(1); | ||
437 | } | ||
438 | |||
439 | if (!timeout) | ||
440 | return SD_ERROR_TIMEOUT; | ||
441 | |||
442 | /* Read data from RXFIFO. It could be FULL or PARTIAL FULL */ | ||
443 | DEBUG("Receive Data = %d", wblocklen); | ||
444 | cnt = wblocklen; | ||
445 | while (cnt) | ||
446 | { | ||
447 | data = REG_MSC_RXFIFO(MSC_CHN(drive)); | ||
448 | if (waligned) | ||
449 | *wbuf++ = data; | ||
450 | else | ||
451 | { | ||
452 | *buf++ = (unsigned char) (data >> 0); | ||
453 | *buf++ = (unsigned char) (data >> 8); | ||
454 | *buf++ = (unsigned char) (data >> 16); | ||
455 | *buf++ = (unsigned char) (data >> 24); | ||
456 | } | ||
457 | cnt--; | ||
458 | while (cnt | ||
459 | && (REG_MSC_STAT(MSC_CHN(drive)) & | ||
460 | MSC_STAT_DATA_FIFO_EMPTY)); | ||
461 | } | ||
462 | } | ||
463 | |||
464 | return SD_NO_ERROR; | ||
465 | } | ||
466 | |||
467 | static int jz_sd_transmit_data(const int drive, struct sd_request *req) | ||
468 | { | ||
469 | unsigned int nob = req->nob; | ||
470 | unsigned int wblocklen = (unsigned int) (req->block_len + 3) >> 2; /* length in word */ | ||
471 | unsigned char *buf = req->buffer; | ||
472 | unsigned int *wbuf = (unsigned int *) buf; | ||
473 | unsigned int waligned = (((unsigned int) buf & 0x3) == 0); /* word aligned ? */ | ||
474 | unsigned int stat, timeout, data, cnt; | ||
475 | |||
476 | for (; nob >= 1; nob--) | ||
477 | { | ||
478 | timeout = 0x3FFFFFF; | ||
479 | |||
480 | while (timeout) | ||
481 | { | ||
482 | timeout--; | ||
483 | stat = REG_MSC_STAT(MSC_CHN(drive)); | ||
484 | |||
485 | if (stat & | ||
486 | (MSC_STAT_CRC_WRITE_ERROR | | ||
487 | MSC_STAT_CRC_WRITE_ERROR_NOSTS)) | ||
488 | return SD_ERROR_CRC; | ||
489 | else if (!(stat & MSC_STAT_DATA_FIFO_FULL)) | ||
490 | /* Ready to write data */ | ||
491 | break; | ||
492 | |||
493 | udelay(1); | ||
494 | } | ||
495 | |||
496 | if (!timeout) | ||
497 | return SD_ERROR_TIMEOUT; | ||
498 | |||
499 | /* Write data to TXFIFO */ | ||
500 | cnt = wblocklen; | ||
501 | while (cnt) | ||
502 | { | ||
503 | while (REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_DATA_FIFO_FULL); | ||
504 | |||
505 | if (waligned) | ||
506 | REG_MSC_TXFIFO(MSC_CHN(drive)) = *wbuf++; | ||
507 | else | ||
508 | { | ||
509 | data = *buf++; | ||
510 | data |= *buf++ << 8; | ||
511 | data |= *buf++ << 16; | ||
512 | data |= *buf++ << 24; | ||
513 | REG_MSC_TXFIFO(MSC_CHN(drive)) = data; | ||
514 | } | ||
515 | |||
516 | cnt--; | ||
517 | } | ||
518 | } | ||
519 | |||
520 | return SD_NO_ERROR; | ||
521 | } | ||
522 | |||
523 | #if SD_DMA_ENABLE | ||
524 | static void jz_sd_receive_data_dma(const int drive, struct sd_request *req) | ||
525 | { | ||
526 | unsigned int waligned = (((unsigned int)req->buffer & 0x3) == 0); /* word aligned ? */ | ||
527 | unsigned int size = req->block_len * req->nob; | ||
528 | |||
529 | if (!waligned) | ||
530 | { | ||
531 | jz_sd_receive_data(drive, req); | ||
532 | return; | ||
533 | } | ||
534 | |||
535 | /* flush dcache */ | ||
536 | dma_cache_wback_inv((unsigned long) req->buffer, size); | ||
537 | |||
538 | /* setup dma channel */ | ||
539 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0; | ||
540 | REG_DMAC_DSAR(DMA_SD_RX_CHANNEL) = PHYSADDR(MSC_RXFIFO(MSC_CHN(drive))); /* DMA source addr */ | ||
541 | REG_DMAC_DTAR(DMA_SD_RX_CHANNEL) = PHYSADDR((unsigned long)req->buffer); /* DMA dest addr */ | ||
542 | REG_DMAC_DTCR(DMA_SD_RX_CHANNEL) = (size + 3) >> 2; /* DMA transfer count */ | ||
543 | REG_DMAC_DRSR(DMA_SD_RX_CHANNEL) = (drive == SD_SLOT_1) ? DMAC_DRSR_RS_MSC2IN : DMAC_DRSR_RS_MSC1IN; /* DMA request type */ | ||
544 | |||
545 | REG_DMAC_DCMD(DMA_SD_RX_CHANNEL) = | ||
546 | DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | | ||
547 | DMAC_DCMD_DS_32BIT; | ||
548 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; | ||
549 | |||
550 | /* wait for dma completion */ | ||
551 | while (REG_DMAC_DTCR(DMA_SD_RX_CHANNEL)); | ||
552 | |||
553 | /* clear status and disable channel */ | ||
554 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0; | ||
555 | } | ||
556 | |||
557 | static void jz_sd_transmit_data_dma(const int drive, struct sd_request *req) | ||
558 | { | ||
559 | unsigned int waligned = (((unsigned int)req->buffer & 0x3) == 0); /* word aligned ? */ | ||
560 | unsigned int size = req->block_len * req->nob; | ||
561 | |||
562 | if (!waligned) | ||
563 | { | ||
564 | jz_sd_transmit_data(drive, req); | ||
565 | return; | ||
566 | } | ||
567 | |||
568 | /* flush dcache */ | ||
569 | dma_cache_wback_inv((unsigned long) req->buffer, size); | ||
570 | |||
571 | /* setup dma channel */ | ||
572 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) = 0; | ||
573 | REG_DMAC_DSAR(DMA_SD_TX_CHANNEL) = PHYSADDR((unsigned long) req->buffer); /* DMA source addr */ | ||
574 | REG_DMAC_DTAR(DMA_SD_TX_CHANNEL) = PHYSADDR(MSC_TXFIFO(MSC_CHN(drive))); /* DMA dest addr */ | ||
575 | REG_DMAC_DTCR(DMA_SD_TX_CHANNEL) = (size + 3) >> 2; /* DMA transfer count */ | ||
576 | REG_DMAC_DRSR(DMA_SD_TX_CHANNEL) = (drive == SD_SLOT_1) ? DMAC_DRSR_RS_MSC2OUT : DMAC_DRSR_RS_MSC1OUT; /* DMA request type */ | ||
577 | |||
578 | REG_DMAC_DCMD(DMA_SD_TX_CHANNEL) = | ||
579 | DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | | ||
580 | DMAC_DCMD_DS_32BIT; | ||
581 | REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES; | ||
582 | |||
583 | /* wait for dma completion */ | ||
584 | while (REG_DMAC_DTCR(DMA_SD_TX_CHANNEL)); | ||
585 | |||
586 | /* clear status and disable channel */ | ||
587 | REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) = 0; | ||
588 | } | ||
589 | |||
590 | void DMA_CALLBACK(DMA_SD_RX_CHANNEL)(void) | ||
591 | { | ||
592 | if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_AR) | ||
593 | { | ||
594 | logf("SD RX DMA address error"); | ||
595 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) &= ~DMAC_DCCSR_AR; | ||
596 | } | ||
597 | |||
598 | if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_HLT) | ||
599 | { | ||
600 | logf("SD RX DMA halt"); | ||
601 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) &= ~DMAC_DCCSR_HLT; | ||
602 | } | ||
603 | |||
604 | if (REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) & DMAC_DCCSR_TT) | ||
605 | { | ||
606 | REG_DMAC_DCCSR(DMA_SD_RX_CHANNEL) &= ~DMAC_DCCSR_TT; | ||
607 | //sd_rx_dma_callback(); | ||
608 | } | ||
609 | } | ||
610 | |||
611 | void DMA_CALLBACK(DMA_SD_TX_CHANNEL)(void) | ||
612 | { | ||
613 | if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_AR) | ||
614 | { | ||
615 | logf("SD TX DMA address error: %x, %x, %x", var1, var2, var3); | ||
616 | REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) &= ~DMAC_DCCSR_AR; | ||
617 | } | ||
618 | |||
619 | if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_HLT) | ||
620 | { | ||
621 | logf("SD TX DMA halt"); | ||
622 | REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) &= ~DMAC_DCCSR_HLT; | ||
623 | } | ||
624 | |||
625 | if (REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) & DMAC_DCCSR_TT) | ||
626 | { | ||
627 | REG_DMAC_DCCSR(DMA_SD_TX_CHANNEL) &= ~DMAC_DCCSR_TT; | ||
628 | //sd_tx_dma_callback(); | ||
629 | } | ||
630 | } | ||
631 | #endif /* SD_DMA_ENABLE */ | ||
632 | |||
633 | static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) | ||
634 | { | ||
635 | unsigned int clkrt; | ||
636 | unsigned int clk_src = sd2_0[drive] ? SD_CLOCK_HIGH : SD_CLOCK_FAST; | ||
637 | |||
638 | clkrt = 0; | ||
639 | while (rate < clk_src) | ||
640 | { | ||
641 | clkrt++; | ||
642 | clk_src >>= 1; | ||
643 | } | ||
644 | return clkrt; | ||
645 | } | ||
646 | |||
647 | static inline void cpm_select_msc_clk(unsigned int rate) | ||
648 | { | ||
649 | unsigned int div = __cpm_get_pllout2() / rate; | ||
650 | |||
651 | REG_CPM_MSCCDR = div - 1; | ||
652 | } | ||
653 | |||
654 | /* Set the MMC clock frequency */ | ||
655 | static void jz_sd_set_clock(const int drive, unsigned int rate) | ||
656 | { | ||
657 | int clkrt; | ||
658 | |||
659 | jz_sd_stop_clock(drive); | ||
660 | |||
661 | /* select clock source from CPM */ | ||
662 | cpm_select_msc_clk(rate); | ||
663 | |||
664 | __cpm_enable_pll_change(); | ||
665 | clkrt = jz_sd_calc_clkrt(drive, rate); | ||
666 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; | ||
667 | |||
668 | DEBUG("set clock to %u Hz clkrt=%d", rate, clkrt); | ||
669 | } | ||
670 | |||
671 | /******************************************************************************************************************** | ||
672 | ** Name: int jz_sd_exec_cmd() | ||
673 | ** Function: send command to the card, and get a response | ||
674 | ** Input: struct sd_request *req: SD request | ||
675 | ** Output: 0: right >0: error code | ||
676 | ********************************************************************************************************************/ | ||
677 | static int jz_sd_exec_cmd(const int drive, struct sd_request *request) | ||
678 | { | ||
679 | unsigned int cmdat = 0, events = 0; | ||
680 | int retval, timeout = 0x3fffff; | ||
681 | |||
682 | /* Indicate we have no result yet */ | ||
683 | request->result = SD_NO_RESPONSE; | ||
684 | |||
685 | if (request->cmd == SD_CIM_RESET) { | ||
686 | /* On reset, 1-bit bus width */ | ||
687 | use_4bit[drive] = 0; | ||
688 | |||
689 | /* Reset MMC/SD controller */ | ||
690 | __msc_reset(MSC_CHN(drive)); | ||
691 | |||
692 | /* On reset, drop SD clock down */ | ||
693 | jz_sd_set_clock(drive, MMC_CLOCK_SLOW); | ||
694 | |||
695 | /* On reset, stop SD clock */ | ||
696 | jz_sd_stop_clock(drive); | ||
697 | } | ||
698 | if (request->cmd == SD_SET_BUS_WIDTH) | ||
699 | { | ||
700 | if (request->arg == 0x2) | ||
701 | { | ||
702 | DEBUG("Use 4-bit bus width"); | ||
703 | use_4bit[drive] = 1; | ||
704 | } | ||
705 | else | ||
706 | { | ||
707 | DEBUG("Use 1-bit bus width"); | ||
708 | use_4bit[drive] = 0; | ||
709 | } | ||
710 | } | ||
711 | |||
712 | /* stop clock */ | ||
713 | jz_sd_stop_clock(drive); | ||
714 | |||
715 | /* mask all interrupts */ | ||
716 | //REG_MSC_IMASK(MSC_CHN(drive)) = 0xffff; | ||
717 | /* clear status */ | ||
718 | REG_MSC_IREG(MSC_CHN(drive)) = 0xffff; | ||
719 | /*open interrupt */ | ||
720 | REG_MSC_IMASK(MSC_CHN(drive)) = (~7); | ||
721 | /* use 4-bit bus width when possible */ | ||
722 | if (use_4bit[drive]) | ||
723 | cmdat |= MSC_CMDAT_BUS_WIDTH_4BIT; | ||
724 | |||
725 | /* Set command type and events */ | ||
726 | switch (request->cmd) | ||
727 | { | ||
728 | /* SD core extra command */ | ||
729 | case SD_CIM_RESET: | ||
730 | cmdat |= MSC_CMDAT_INIT; /* Initialization sequence sent prior to command */ | ||
731 | break; | ||
732 | /* bc - broadcast - no response */ | ||
733 | case SD_GO_IDLE_STATE: | ||
734 | case SD_SET_DSR: | ||
735 | break; | ||
736 | |||
737 | /* bcr - broadcast with response */ | ||
738 | case SD_APP_OP_COND: | ||
739 | case SD_ALL_SEND_CID: | ||
740 | case SD_GO_IRQ_STATE: | ||
741 | break; | ||
742 | |||
743 | /* adtc - addressed with data transfer */ | ||
744 | case SD_READ_DAT_UNTIL_STOP: | ||
745 | case SD_READ_SINGLE_BLOCK: | ||
746 | case SD_READ_MULTIPLE_BLOCK: | ||
747 | case SD_SEND_SCR: | ||
748 | #if SD_DMA_ENABLE | ||
749 | cmdat |= | ||
750 | MSC_CMDAT_DATA_EN | MSC_CMDAT_READ | MSC_CMDAT_DMA_EN; | ||
751 | #else | ||
752 | cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ; | ||
753 | #endif | ||
754 | events = SD_EVENT_RX_DATA_DONE; | ||
755 | break; | ||
756 | |||
757 | case 6: | ||
758 | if (num_6[drive] < 2) | ||
759 | { | ||
760 | #if SD_DMA_ENABLE | ||
761 | cmdat |= | ||
762 | MSC_CMDAT_DATA_EN | MSC_CMDAT_READ | | ||
763 | MSC_CMDAT_DMA_EN; | ||
764 | #else | ||
765 | cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_READ; | ||
766 | #endif | ||
767 | events = SD_EVENT_RX_DATA_DONE; | ||
768 | } | ||
769 | break; | ||
770 | |||
771 | case SD_WRITE_DAT_UNTIL_STOP: | ||
772 | case SD_WRITE_BLOCK: | ||
773 | case SD_WRITE_MULTIPLE_BLOCK: | ||
774 | case SD_PROGRAM_CID: | ||
775 | case SD_PROGRAM_CSD: | ||
776 | case SD_LOCK_UNLOCK: | ||
777 | #if SD_DMA_ENABLE | ||
778 | cmdat |= | ||
779 | MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE | MSC_CMDAT_DMA_EN; | ||
780 | #else | ||
781 | cmdat |= MSC_CMDAT_DATA_EN | MSC_CMDAT_WRITE; | ||
782 | #endif | ||
783 | events = SD_EVENT_TX_DATA_DONE | SD_EVENT_PROG_DONE; | ||
784 | break; | ||
785 | |||
786 | case SD_STOP_TRANSMISSION: | ||
787 | events = SD_EVENT_PROG_DONE; | ||
788 | break; | ||
789 | |||
790 | /* ac - no data transfer */ | ||
791 | default: | ||
792 | break; | ||
793 | } | ||
794 | |||
795 | /* Set response type */ | ||
796 | switch (request->rtype) | ||
797 | { | ||
798 | case RESPONSE_NONE: | ||
799 | break; | ||
800 | case RESPONSE_R1B: | ||
801 | cmdat |= MSC_CMDAT_BUSY; | ||
802 | /* FALLTHRU */ | ||
803 | case RESPONSE_R1: | ||
804 | case RESPONSE_R7: | ||
805 | cmdat |= MSC_CMDAT_RESPONSE_R1; | ||
806 | break; | ||
807 | case RESPONSE_R2_CID: | ||
808 | case RESPONSE_R2_CSD: | ||
809 | cmdat |= MSC_CMDAT_RESPONSE_R2; | ||
810 | break; | ||
811 | case RESPONSE_R3: | ||
812 | cmdat |= MSC_CMDAT_RESPONSE_R3; | ||
813 | break; | ||
814 | case RESPONSE_R4: | ||
815 | cmdat |= MSC_CMDAT_RESPONSE_R4; | ||
816 | break; | ||
817 | case RESPONSE_R5: | ||
818 | cmdat |= MSC_CMDAT_RESPONSE_R5; | ||
819 | break; | ||
820 | case RESPONSE_R6: | ||
821 | cmdat |= MSC_CMDAT_RESPONSE_R6; | ||
822 | break; | ||
823 | default: | ||
824 | break; | ||
825 | } | ||
826 | |||
827 | /* Set command index */ | ||
828 | if (request->cmd == SD_CIM_RESET) | ||
829 | REG_MSC_CMD(MSC_CHN(drive)) = SD_GO_IDLE_STATE; | ||
830 | else | ||
831 | REG_MSC_CMD(MSC_CHN(drive)) = request->cmd; | ||
832 | |||
833 | /* Set argument */ | ||
834 | REG_MSC_ARG(MSC_CHN(drive)) = request->arg; | ||
835 | |||
836 | /* Set block length and nob */ | ||
837 | if (request->cmd == SD_SEND_SCR) | ||
838 | { /* get SCR from DataFIFO */ | ||
839 | REG_MSC_BLKLEN(MSC_CHN(drive)) = 8; | ||
840 | REG_MSC_NOB(MSC_CHN(drive)) = 1; | ||
841 | } | ||
842 | else | ||
843 | { | ||
844 | REG_MSC_BLKLEN(MSC_CHN(drive)) = request->block_len; | ||
845 | REG_MSC_NOB(MSC_CHN(drive)) = request->nob; | ||
846 | } | ||
847 | |||
848 | /* Set command */ | ||
849 | REG_MSC_CMDAT(MSC_CHN(drive)) = cmdat; | ||
850 | |||
851 | DEBUG("Send cmd %d cmdat: %x arg: %x resp %d", request->cmd, | ||
852 | cmdat, request->arg, request->rtype); | ||
853 | |||
854 | /* Start SD clock and send command to card */ | ||
855 | jz_sd_start_clock(drive); | ||
856 | |||
857 | /* Wait for command completion */ | ||
858 | //__intc_unmask_irq(IRQ_MSC); | ||
859 | //semaphore_wait(&sd_wakeup, 100); | ||
860 | while (timeout-- && !(REG_MSC_STAT(MSC_CHN(drive)) & MSC_STAT_END_CMD_RES)); | ||
861 | |||
862 | |||
863 | if (timeout == 0) | ||
864 | return SD_ERROR_TIMEOUT; | ||
865 | |||
866 | REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_END_CMD_RES; /* clear flag */ | ||
867 | |||
868 | /* Check for status */ | ||
869 | retval = jz_sd_check_status(drive, request); | ||
870 | if (retval) | ||
871 | return retval; | ||
872 | |||
873 | /* Complete command with no response */ | ||
874 | if (request->rtype == RESPONSE_NONE) | ||
875 | return SD_NO_ERROR; | ||
876 | |||
877 | /* Get response */ | ||
878 | jz_sd_get_response(drive, request); | ||
879 | |||
880 | /* Start data operation */ | ||
881 | if (events & (SD_EVENT_RX_DATA_DONE | SD_EVENT_TX_DATA_DONE)) | ||
882 | { | ||
883 | if (events & SD_EVENT_RX_DATA_DONE) | ||
884 | { | ||
885 | if (request->cmd == SD_SEND_SCR) | ||
886 | { | ||
887 | /* SD card returns SCR register as data. | ||
888 | SD core expect it in the response buffer, | ||
889 | after normal response. */ | ||
890 | request->buffer = | ||
891 | (unsigned char *) ((unsigned int) request->response + 5); | ||
892 | } | ||
893 | #if SD_DMA_ENABLE | ||
894 | jz_sd_receive_data_dma(drive, request); | ||
895 | #else | ||
896 | jz_sd_receive_data(drive, request); | ||
897 | #endif | ||
898 | } | ||
899 | |||
900 | if (events & SD_EVENT_TX_DATA_DONE) | ||
901 | { | ||
902 | #if SD_DMA_ENABLE | ||
903 | jz_sd_transmit_data_dma(drive, request); | ||
904 | #else | ||
905 | jz_sd_transmit_data(drive, request); | ||
906 | #endif | ||
907 | } | ||
908 | //__intc_unmask_irq(IRQ_MSC); | ||
909 | //semaphore_wait(&sd_wakeup, 100); | ||
910 | /* Wait for Data Done */ | ||
911 | while (!(REG_MSC_IREG(MSC_CHN(drive)) & MSC_IREG_DATA_TRAN_DONE)); | ||
912 | REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_DATA_TRAN_DONE; /* clear status */ | ||
913 | } | ||
914 | |||
915 | /* Wait for Prog Done event */ | ||
916 | if (events & SD_EVENT_PROG_DONE) | ||
917 | { | ||
918 | //__intc_unmask_irq(IRQ_MSC); | ||
919 | //semaphore_wait(&sd_wakeup, 100); | ||
920 | while (!(REG_MSC_IREG(MSC_CHN(drive)) & MSC_IREG_PRG_DONE)); | ||
921 | REG_MSC_IREG(MSC_CHN(drive)) = MSC_IREG_PRG_DONE; /* clear status */ | ||
922 | } | ||
923 | |||
924 | /* Command completed */ | ||
925 | |||
926 | return SD_NO_ERROR; /* return successfully */ | ||
927 | } | ||
928 | |||
929 | /******************************************************************************************************************* | ||
930 | ** Name: int sd_chkcard() | ||
931 | ** Function: check whether card is insert entirely | ||
932 | ** Input: NULL | ||
933 | ** Output: 1: insert entirely 0: not insert entirely | ||
934 | ********************************************************************************************************************/ | ||
935 | static int jz_sd_chkcard(const int drive) | ||
936 | { | ||
937 | return (__gpio_get_pin((drive == SD_SLOT_1) ? PIN_SD1_CD : PIN_SD2_CD) == 0 ? 1 : 0); | ||
938 | } | ||
939 | |||
940 | /* MSC interrupt handler */ | ||
941 | void MSC(void) | ||
942 | { | ||
943 | //semaphore_release(&sd_wakeup); | ||
944 | logf("MSC interrupt"); | ||
945 | } | ||
946 | |||
947 | #ifdef HAVE_HOTSWAP | ||
948 | static void sd_gpio_setup_irq(const int drive, bool inserted) | ||
949 | { | ||
950 | int pin = (drive == SD_SLOT_1) ? PIN_SD1_CD : PIN_SD2_CD; | ||
951 | int irq = (drive == SD_SLOT_1) ? IRQ_SD1_CD : IRQ_SD2_CD; | ||
952 | if(inserted) | ||
953 | __gpio_as_irq_rise_edge(pin); | ||
954 | else | ||
955 | __gpio_as_irq_fall_edge(pin); | ||
956 | system_enable_irq(irq); | ||
957 | } | ||
958 | #endif | ||
959 | |||
960 | /******************************************************************************************************************* | ||
961 | ** Name: void sd_hardware_init() | ||
962 | ** Function: initialize the hardware condiction that access sd card | ||
963 | ** Input: NULL | ||
964 | ** Output: NULL | ||
965 | ********************************************************************************************************************/ | ||
966 | static void jz_sd_hardware_init(const int drive) | ||
967 | { | ||
968 | if (drive == SD_SLOT_1) | ||
969 | __cpm_start_msc2(); /* enable mmc2 clock */ | ||
970 | else | ||
971 | __cpm_start_msc1(); /* enable mmc1 clock */ | ||
972 | #ifdef HAVE_HOTSWAP | ||
973 | sd_gpio_setup_irq(drive, jz_sd_chkcard(drive)); | ||
974 | #endif | ||
975 | __msc_reset(MSC_CHN(drive)); /* reset mmc/sd controller */ | ||
976 | SD_IRQ_MASK(MSC_CHN(drive)); /* mask all IRQs */ | ||
977 | jz_sd_stop_clock(drive); /* stop SD clock */ | ||
978 | } | ||
979 | |||
980 | static int sd_send_cmd(const int drive, struct sd_request *request, int cmd, unsigned int arg, | ||
981 | unsigned short nob, unsigned short block_len, | ||
982 | enum sd_rsp_t rtype, unsigned char* buffer) | ||
983 | { | ||
984 | request->cmd = cmd; | ||
985 | request->arg = arg; | ||
986 | request->rtype = rtype; | ||
987 | request->nob = nob; | ||
988 | request->block_len = block_len; | ||
989 | request->buffer = buffer; | ||
990 | request->cnt = nob * block_len; | ||
991 | |||
992 | return jz_sd_exec_cmd(drive, request); | ||
993 | } | ||
994 | |||
995 | static void sd_simple_cmd(const int drive, struct sd_request *request, int cmd, unsigned int arg, | ||
996 | enum sd_rsp_t rtype) | ||
997 | { | ||
998 | sd_send_cmd(drive, request, cmd, arg, 0, 0, rtype, NULL); | ||
999 | } | ||
1000 | |||
1001 | #define SD_INIT_DOING 0 | ||
1002 | #define SD_INIT_PASSED 1 | ||
1003 | #define SD_INIT_FAILED 2 | ||
1004 | static int sd_init_card_state(const int drive, struct sd_request *request) | ||
1005 | { | ||
1006 | struct sd_response_r1 r1; | ||
1007 | struct sd_response_r3 r3; | ||
1008 | int retval, i, ocr = 0x40300000, limit_41 = 0; | ||
1009 | |||
1010 | switch (request->cmd) | ||
1011 | { | ||
1012 | case SD_GO_IDLE_STATE: /* No response to parse */ | ||
1013 | sd_simple_cmd(drive, request, SD_SEND_IF_COND, 0x1AA, RESPONSE_R1); | ||
1014 | break; | ||
1015 | |||
1016 | case SD_SEND_IF_COND: | ||
1017 | retval = sd_unpack_r1(request, &r1); | ||
1018 | sd_simple_cmd(drive, request, SD_APP_CMD, 0, RESPONSE_R1); | ||
1019 | break; | ||
1020 | |||
1021 | case SD_APP_CMD: | ||
1022 | retval = sd_unpack_r1(request, &r1); | ||
1023 | if (retval & (limit_41 < 100)) | ||
1024 | { | ||
1025 | DEBUG("sd_init_card_state: unable to SD_APP_CMD error=%d", | ||
1026 | retval); | ||
1027 | limit_41++; | ||
1028 | sd_simple_cmd(drive, request, SD_APP_OP_COND, ocr, RESPONSE_R3); | ||
1029 | } | ||
1030 | else if (limit_41 < 100) | ||
1031 | { | ||
1032 | limit_41++; | ||
1033 | sd_simple_cmd(drive, request, SD_APP_OP_COND, ocr, RESPONSE_R3); | ||
1034 | } | ||
1035 | else | ||
1036 | /* reset the card to idle*/ | ||
1037 | sd_simple_cmd(drive, request, SD_GO_IDLE_STATE, 0, RESPONSE_NONE); | ||
1038 | break; | ||
1039 | |||
1040 | case SD_APP_OP_COND: | ||
1041 | retval = sd_unpack_r3(request, &r3); | ||
1042 | if (retval) | ||
1043 | break; | ||
1044 | |||
1045 | DEBUG("sd_init_card_state: read ocr value = 0x%08x", r3.ocr); | ||
1046 | card[drive].ocr = r3.ocr; | ||
1047 | |||
1048 | if(!(r3.ocr & SD_CARD_BUSY || ocr == 0)) | ||
1049 | { | ||
1050 | sleep(HZ / 100); | ||
1051 | sd_simple_cmd(drive, request, SD_APP_CMD, 0, RESPONSE_R1); | ||
1052 | } | ||
1053 | else | ||
1054 | { | ||
1055 | /* Set the data bus width to 4 bits */ | ||
1056 | use_4bit[drive] = 1; | ||
1057 | sd_simple_cmd(drive, request, SD_ALL_SEND_CID, 0, RESPONSE_R2_CID); | ||
1058 | } | ||
1059 | break; | ||
1060 | |||
1061 | case SD_ALL_SEND_CID: | ||
1062 | for(i=0; i<4; i++) | ||
1063 | card[drive].cid[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) | | ||
1064 | (request->response[3+i*4]<< 8) | request->response[4+i*4]); | ||
1065 | |||
1066 | logf("CID: %08lx%08lx%08lx%08lx", card[drive].cid[0], card[drive].cid[1], card[drive].cid[2], card[drive].cid[3]); | ||
1067 | sd_simple_cmd(drive, request, SD_SEND_RELATIVE_ADDR, 0, RESPONSE_R6); | ||
1068 | break; | ||
1069 | case SD_SEND_RELATIVE_ADDR: | ||
1070 | retval = sd_unpack_r6(request, &r1, &card[drive].rca); | ||
1071 | card[drive].rca = card[drive].rca << 16; | ||
1072 | DEBUG("sd_init_card_state: Get RCA from SD: 0x%04lx Status: %x", card[drive].rca, r1.status); | ||
1073 | if (retval) | ||
1074 | { | ||
1075 | DEBUG("sd_init_card_state: unable to SET_RELATIVE_ADDR error=%d", | ||
1076 | retval); | ||
1077 | return SD_INIT_FAILED; | ||
1078 | } | ||
1079 | |||
1080 | sd_simple_cmd(drive, request, SD_SEND_CSD, card[drive].rca, RESPONSE_R2_CSD); | ||
1081 | break; | ||
1082 | |||
1083 | case SD_SEND_CSD: | ||
1084 | for(i=0; i<4; i++) | ||
1085 | card[drive].csd[i] = ((request->response[1+i*4]<<24) | (request->response[2+i*4]<<16) | | ||
1086 | (request->response[3+i*4]<< 8) | request->response[4+i*4]); | ||
1087 | |||
1088 | sd_parse_csd(&card[drive]); | ||
1089 | sd2_0[drive] = (card_extract_bits(card[drive].csd, 127, 2) == 1); | ||
1090 | |||
1091 | logf("CSD: %08lx%08lx%08lx%08lx", card[drive].csd[0], card[drive].csd[1], card[drive].csd[2], card[drive].csd[3]); | ||
1092 | DEBUG("SD card is ready"); | ||
1093 | jz_sd_set_clock(drive, SD_CLOCK_FAST); | ||
1094 | return SD_INIT_PASSED; | ||
1095 | |||
1096 | default: | ||
1097 | DEBUG("sd_init_card_state: error! Illegal last cmd %d", request->cmd); | ||
1098 | return SD_INIT_FAILED; | ||
1099 | } | ||
1100 | |||
1101 | return SD_INIT_DOING; | ||
1102 | } | ||
1103 | |||
1104 | static int sd_switch(const int drive, struct sd_request *request, int mode, int group, | ||
1105 | unsigned char value, unsigned char * resp) | ||
1106 | { | ||
1107 | unsigned int arg; | ||
1108 | |||
1109 | mode = !!mode; | ||
1110 | value &= 0xF; | ||
1111 | arg = (mode << 31 | 0x00FFFFFF); | ||
1112 | arg &= ~(0xF << (group * 4)); | ||
1113 | arg |= value << (group * 4); | ||
1114 | sd_send_cmd(drive, request, 6, arg, 1, 64, RESPONSE_R1, resp); | ||
1115 | |||
1116 | return 0; | ||
1117 | } | ||
1118 | |||
1119 | /* | ||
1120 | * Fetches and decodes switch information | ||
1121 | */ | ||
1122 | static int sd_read_switch(const int drive, struct sd_request *request) | ||
1123 | { | ||
1124 | unsigned int status[64 / 4]; | ||
1125 | |||
1126 | memset((unsigned char *)status, 0, 64); | ||
1127 | sd_switch(drive, request, 0, 0, 1, (unsigned char*) status); | ||
1128 | |||
1129 | if (((unsigned char *)status)[13] & 0x02) | ||
1130 | return 0; | ||
1131 | else | ||
1132 | return 1; | ||
1133 | } | ||
1134 | |||
1135 | /* | ||
1136 | * Test if the card supports high-speed mode and, if so, switch to it. | ||
1137 | */ | ||
1138 | static int sd_switch_hs(const int drive, struct sd_request *request) | ||
1139 | { | ||
1140 | unsigned int status[64 / 4]; | ||
1141 | |||
1142 | sd_switch(drive, request, 1, 0, 1, (unsigned char*) status); | ||
1143 | return 0; | ||
1144 | } | ||
1145 | |||
1146 | static int sd_select_card(const int drive) | ||
1147 | { | ||
1148 | struct sd_request request; | ||
1149 | struct sd_response_r1 r1; | ||
1150 | int retval; | ||
1151 | |||
1152 | sd_simple_cmd(drive, &request, SD_SELECT_CARD, card[drive].rca, | ||
1153 | RESPONSE_R1B); | ||
1154 | retval = sd_unpack_r1(&request, &r1); | ||
1155 | if (retval) | ||
1156 | return retval; | ||
1157 | |||
1158 | if (sd2_0[drive]) | ||
1159 | { | ||
1160 | retval = sd_read_switch(drive, &request); | ||
1161 | if (!retval) | ||
1162 | { | ||
1163 | sd_switch_hs(drive, &request); | ||
1164 | jz_sd_set_clock(drive, SD_CLOCK_HIGH); | ||
1165 | } | ||
1166 | } | ||
1167 | num_6[drive] = 3; | ||
1168 | sd_simple_cmd(drive, &request, SD_APP_CMD, card[drive].rca, | ||
1169 | RESPONSE_R1); | ||
1170 | retval = sd_unpack_r1(&request, &r1); | ||
1171 | if (retval) | ||
1172 | return retval; | ||
1173 | sd_simple_cmd(drive, &request, SD_SET_BUS_WIDTH, 2, RESPONSE_R1); | ||
1174 | retval = sd_unpack_r1(&request, &r1); | ||
1175 | if (retval) | ||
1176 | return retval; | ||
1177 | |||
1178 | card[drive].initialized = 1; | ||
1179 | |||
1180 | return 0; | ||
1181 | } | ||
1182 | |||
1183 | static int sd_init_device(const int drive) | ||
1184 | { | ||
1185 | int retval = 0; | ||
1186 | struct sd_request init_req; | ||
1187 | register int timeout = 1000; | ||
1188 | |||
1189 | mutex_lock(&sd_mtx); | ||
1190 | |||
1191 | /* Initialise card data as blank */ | ||
1192 | memset(&card[drive], 0, sizeof(tCardInfo)); | ||
1193 | |||
1194 | sd2_0[drive] = 0; | ||
1195 | num_6[drive] = 0; | ||
1196 | use_4bit[drive] = 0; | ||
1197 | |||
1198 | /* reset mmc/sd controller */ | ||
1199 | jz_sd_hardware_init(drive); | ||
1200 | |||
1201 | sd_simple_cmd(drive, &init_req, SD_CIM_RESET, 0, RESPONSE_NONE); | ||
1202 | sd_simple_cmd(drive, &init_req, SD_GO_IDLE_STATE, 0, RESPONSE_NONE); | ||
1203 | |||
1204 | sleep(HZ/2); /* Give the card/controller some rest */ | ||
1205 | |||
1206 | while(timeout-- && ((retval = sd_init_card_state(drive, &init_req)) == SD_INIT_DOING)); | ||
1207 | retval = (retval == SD_INIT_PASSED ? sd_select_card(drive) : -1); | ||
1208 | |||
1209 | if (drive == SD_SLOT_1) | ||
1210 | __cpm_stop_msc2(); /* disable SD1 clock */ | ||
1211 | else | ||
1212 | __cpm_stop_msc1(); /* disable SD2 clock */ | ||
1213 | |||
1214 | mutex_unlock(&sd_mtx); | ||
1215 | |||
1216 | return retval; | ||
1217 | } | ||
1218 | |||
1219 | int sd_init(void) | ||
1220 | { | ||
1221 | static bool inited = false; | ||
1222 | |||
1223 | sd_init_gpio(); /* init GPIO */ | ||
1224 | |||
1225 | #if SD_DMA_ENABLE | ||
1226 | __dmac_channel_enable_clk(DMA_SD_RX_CHANNEL); | ||
1227 | __dmac_channel_enable_clk(DMA_SD_TX_CHANNEL); | ||
1228 | #endif | ||
1229 | |||
1230 | if(!inited) | ||
1231 | { | ||
1232 | semaphore_init(&sd_wakeup, 1, 0); | ||
1233 | mutex_init(&sd_mtx); | ||
1234 | inited = true; | ||
1235 | } | ||
1236 | |||
1237 | for (int drive = 0; drive < NUM_DRIVES; drive++) | ||
1238 | sd_init_device(drive); | ||
1239 | |||
1240 | return 0; | ||
1241 | } | ||
1242 | |||
1243 | static inline bool card_detect_target(const int drive) | ||
1244 | { | ||
1245 | return (jz_sd_chkcard(drive) == 1); | ||
1246 | } | ||
1247 | |||
1248 | tCardInfo* card_get_info_target(const int drive) | ||
1249 | { | ||
1250 | return &card[drive]; | ||
1251 | } | ||
1252 | |||
1253 | static inline void sd_start_transfer(const int drive) | ||
1254 | { | ||
1255 | mutex_lock(&sd_mtx); | ||
1256 | if (drive == SD_SLOT_1) | ||
1257 | __cpm_start_msc2(); | ||
1258 | else | ||
1259 | __cpm_start_msc1(); | ||
1260 | led(true); | ||
1261 | } | ||
1262 | |||
1263 | static inline void sd_stop_transfer(const int drive) | ||
1264 | { | ||
1265 | led(false); | ||
1266 | if (drive == SD_SLOT_1) | ||
1267 | __cpm_stop_msc2(); | ||
1268 | else | ||
1269 | __cpm_stop_msc1(); | ||
1270 | mutex_unlock(&sd_mtx); | ||
1271 | } | ||
1272 | |||
1273 | int sd_read_sectors(const int drive, unsigned long start, int count, void* buf) | ||
1274 | { | ||
1275 | sd_start_transfer(drive); | ||
1276 | |||
1277 | struct sd_request request; | ||
1278 | struct sd_response_r1 r1; | ||
1279 | int retval = -1; | ||
1280 | |||
1281 | if (!card_detect_target(drive) || count == 0 || start > card[drive].numblocks) | ||
1282 | goto err; | ||
1283 | |||
1284 | if(card[drive].initialized == 0 && !sd_init_device(drive)) | ||
1285 | goto err; | ||
1286 | |||
1287 | sd_simple_cmd(drive, &request, SD_SEND_STATUS, card[drive].rca, RESPONSE_R1); | ||
1288 | retval = sd_unpack_r1(&request, &r1); | ||
1289 | if (retval && (retval != SD_ERROR_STATE_MISMATCH)) | ||
1290 | goto err; | ||
1291 | |||
1292 | sd_simple_cmd(drive, &request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1); | ||
1293 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1294 | goto err; | ||
1295 | |||
1296 | if (sd2_0[drive]) | ||
1297 | { | ||
1298 | sd_send_cmd(drive, &request, SD_READ_MULTIPLE_BLOCK, start, | ||
1299 | count, SD_BLOCK_SIZE, RESPONSE_R1, buf); | ||
1300 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1301 | goto err; | ||
1302 | } | ||
1303 | else | ||
1304 | { | ||
1305 | sd_send_cmd(drive, &request, SD_READ_MULTIPLE_BLOCK, | ||
1306 | start * SD_BLOCK_SIZE, count, | ||
1307 | SD_BLOCK_SIZE, RESPONSE_R1, buf); | ||
1308 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1309 | goto err; | ||
1310 | } | ||
1311 | |||
1312 | last_disk_activity = current_tick; | ||
1313 | |||
1314 | sd_simple_cmd(drive, &request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B); | ||
1315 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1316 | goto err; | ||
1317 | |||
1318 | err: | ||
1319 | sd_stop_transfer(drive); | ||
1320 | |||
1321 | return retval; | ||
1322 | } | ||
1323 | |||
1324 | int sd_write_sectors(const int drive, unsigned long start, int count, const void* buf) | ||
1325 | { | ||
1326 | sd_start_transfer(drive); | ||
1327 | |||
1328 | struct sd_request request; | ||
1329 | struct sd_response_r1 r1; | ||
1330 | int retval = -1; | ||
1331 | |||
1332 | if (!card_detect_target(drive) || count == 0 || start > card[drive].numblocks) | ||
1333 | goto err; | ||
1334 | |||
1335 | if(card[drive].initialized == 0 && !sd_init_device(drive)) | ||
1336 | goto err; | ||
1337 | |||
1338 | sd_simple_cmd(drive, &request, SD_SEND_STATUS, card[drive].rca, RESPONSE_R1); | ||
1339 | retval = sd_unpack_r1(&request, &r1); | ||
1340 | if (retval && (retval != SD_ERROR_STATE_MISMATCH)) | ||
1341 | goto err; | ||
1342 | |||
1343 | sd_simple_cmd(drive, &request, SD_SET_BLOCKLEN, SD_BLOCK_SIZE, RESPONSE_R1); | ||
1344 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1345 | goto err; | ||
1346 | |||
1347 | if (sd2_0[drive]) | ||
1348 | { | ||
1349 | sd_send_cmd(drive, &request, SD_WRITE_MULTIPLE_BLOCK, start, | ||
1350 | count, SD_BLOCK_SIZE, RESPONSE_R1, | ||
1351 | (void*)buf); | ||
1352 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1353 | goto err; | ||
1354 | } | ||
1355 | else | ||
1356 | { | ||
1357 | sd_send_cmd(drive, &request, SD_WRITE_MULTIPLE_BLOCK, | ||
1358 | start * SD_BLOCK_SIZE, count, | ||
1359 | SD_BLOCK_SIZE, RESPONSE_R1, (void*)buf); | ||
1360 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1361 | goto err; | ||
1362 | } | ||
1363 | |||
1364 | last_disk_activity = current_tick; | ||
1365 | |||
1366 | sd_simple_cmd(drive, &request, SD_STOP_TRANSMISSION, 0, RESPONSE_R1B); | ||
1367 | if ((retval = sd_unpack_r1(&request, &r1))) | ||
1368 | goto err; | ||
1369 | |||
1370 | err: | ||
1371 | sd_stop_transfer(drive); | ||
1372 | |||
1373 | return retval; | ||
1374 | } | ||
1375 | |||
1376 | long sd_last_disk_activity(void) | ||
1377 | { | ||
1378 | return last_disk_activity; | ||
1379 | } | ||
1380 | |||
1381 | int sd_spinup_time(void) | ||
1382 | { | ||
1383 | return 0; | ||
1384 | } | ||
1385 | |||
1386 | void sd_enable(bool on) | ||
1387 | { | ||
1388 | (void)on; | ||
1389 | } | ||
1390 | |||
1391 | bool sd_disk_is_active(void) | ||
1392 | { | ||
1393 | return false; | ||
1394 | } | ||
1395 | |||
1396 | int sd_soft_reset(void) | ||
1397 | { | ||
1398 | return 0; | ||
1399 | } | ||
1400 | |||
1401 | #ifdef HAVE_HOTSWAP | ||
1402 | bool sd_removable(const int drive) | ||
1403 | { | ||
1404 | (void)drive; | ||
1405 | return true; | ||
1406 | } | ||
1407 | |||
1408 | static int sd1_oneshot_callback(struct timeout *tmo) | ||
1409 | { | ||
1410 | int state = card_detect_target(SD_SLOT_1); | ||
1411 | |||
1412 | /* This is called only if the state was stable for 300ms - check state | ||
1413 | * and post appropriate event. */ | ||
1414 | queue_broadcast(state ? SYS_HOTSWAP_INSERTED : SYS_HOTSWAP_EXTRACTED, | ||
1415 | 0); | ||
1416 | |||
1417 | sd_gpio_setup_irq(SD_SLOT_1, state); | ||
1418 | |||
1419 | return 0; | ||
1420 | (void)tmo; | ||
1421 | } | ||
1422 | |||
1423 | static int sd2_oneshot_callback(struct timeout *tmo) | ||
1424 | { | ||
1425 | int state = card_detect_target(SD_SLOT_2); | ||
1426 | |||
1427 | /* This is called only if the state was stable for 300ms - check state | ||
1428 | * and post appropriate event. */ | ||
1429 | queue_broadcast(state ? SYS_HOTSWAP_INSERTED : SYS_HOTSWAP_EXTRACTED, | ||
1430 | 1); | ||
1431 | |||
1432 | sd_gpio_setup_irq(SD_SLOT_2, state); | ||
1433 | |||
1434 | return 0; | ||
1435 | (void)tmo; | ||
1436 | } | ||
1437 | |||
1438 | /* called on insertion/removal interrupt */ | ||
1439 | void GPIO_SD1_CD(void) | ||
1440 | { | ||
1441 | static struct timeout sd1_oneshot; | ||
1442 | timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0); | ||
1443 | } | ||
1444 | |||
1445 | void GPIO_SD2_CD(void) | ||
1446 | { | ||
1447 | static struct timeout sd2_oneshot; | ||
1448 | timeout_register(&sd2_oneshot, sd2_oneshot_callback, (3*HZ/10), 0); | ||
1449 | } | ||
1450 | #endif | ||
1451 | |||
1452 | bool sd_present(const int drive) | ||
1453 | { | ||
1454 | return card_detect_target(drive); | ||
1455 | } | ||
1456 | |||
1457 | #ifdef CONFIG_STORAGE_MULTI | ||
1458 | int sd_num_drives(int first_drive) | ||
1459 | { | ||
1460 | return NUM_DRIVES; | ||
1461 | } | ||
1462 | #endif /* CONFIG_STORAGE_MULTI */ | ||
1463 | |||
1464 | int sd_event(long id, intptr_t data) | ||
1465 | { | ||
1466 | int rc = 0; | ||
1467 | |||
1468 | switch (id) | ||
1469 | { | ||
1470 | #ifdef HAVE_HOTSWAP | ||
1471 | case SYS_HOTSWAP_INSERTED: | ||
1472 | case SYS_HOTSWAP_EXTRACTED: | ||
1473 | /* Force card init for new card, re-init for re-inserted one or | ||
1474 | * clear if the last attempt to init failed with an error. */ | ||
1475 | mutex_lock(&sd_mtx); /* lock-out card activity */ | ||
1476 | card[data].initialized = 0; | ||
1477 | mutex_unlock(&sd_mtx); | ||
1478 | break; | ||
1479 | #endif /* HAVE_HOTSWAP */ | ||
1480 | default: | ||
1481 | rc = storage_event_default_handler(id, data, last_disk_activity, | ||
1482 | STORAGE_SD); | ||
1483 | break; | ||
1484 | } | ||
1485 | |||
1486 | return rc; | ||
1487 | } | ||