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author | Marcin Bukat <marcin.bukat@gmail.com> | 2010-04-26 21:40:00 +0000 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2010-04-26 21:40:00 +0000 |
commit | b09d3aec392538ca0934644ff6357c41aaa4c323 (patch) | |
tree | 0603cf4ef59e84ee4e0c172e3b418d8dccac664c /firmware/target/coldfire | |
parent | fa5cd0d3bf744f75be0593a7e2c2083810f16c21 (diff) | |
download | rockbox-b09d3aec392538ca0934644ff6357c41aaa4c323.tar.gz rockbox-b09d3aec392538ca0934644ff6357c41aaa4c323.zip |
Add MPIO HD200 port - changed files
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25724 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire')
-rw-r--r-- | firmware/target/coldfire/crt0.S | 19 | ||||
-rw-r--r-- | firmware/target/coldfire/i2c-coldfire.c | 4 | ||||
-rw-r--r-- | firmware/target/coldfire/pcm-coldfire.c | 30 | ||||
-rw-r--r-- | firmware/target/coldfire/system-coldfire.c | 5 |
4 files changed, 57 insertions, 1 deletions
diff --git a/firmware/target/coldfire/crt0.S b/firmware/target/coldfire/crt0.S index bc8a370823..38365c7d71 100644 --- a/firmware/target/coldfire/crt0.S +++ b/firmware/target/coldfire/crt0.S | |||
@@ -63,7 +63,16 @@ start: | |||
63 | move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */ | 63 | move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */ |
64 | move.l %d0,(0x088,%a0) | 64 | move.l %d0,(0x088,%a0) |
65 | 65 | ||
66 | #ifndef IAUDIO_M3 | 66 | #ifdef MPIO_HD200 |
67 | /* Chip select 3 - LCD controller */ | ||
68 | /* values taken from original firmware except base address*/ | ||
69 | move.l #0xf0000000,%d0 /* CSAR3 - Base = 0xf0000000 */ | ||
70 | move.l %d0,(0x0a4,%a0) | ||
71 | moveq.l #0x1,%d0 /* CSMR3 - 64K */ | ||
72 | move.l %d0,(0x0a8,%a0) | ||
73 | move.l #0x00000980,%d0 /* CSCR3 - 1 wait state, 16 bits no bursts */ | ||
74 | move.l %d0,(0x0ac,%a0) | ||
75 | #elif !(defined IAUDIO_M3) | ||
67 | /* Chip select 1 - LCD controller */ | 76 | /* Chip select 1 - LCD controller */ |
68 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ | 77 | move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */ |
69 | move.l %d0,(0x08c,%a0) | 78 | move.l %d0,(0x08c,%a0) |
@@ -267,6 +276,14 @@ start: | |||
267 | or.l %d0,(0xbc,%a1) | 276 | or.l %d0,(0xbc,%a1) |
268 | #endif | 277 | #endif |
269 | 278 | ||
279 | #ifdef MPIO_HD200 | ||
280 | /* Set KEEP_ACT */ | ||
281 | move.l #0x02200000,%d0 | ||
282 | or.l %d0,(0xb4,%a1) | ||
283 | or.l %d0,(0xb8,%a1) | ||
284 | or.l %d0,(0xbc,%a1) | ||
285 | #endif | ||
286 | |||
270 | /* zero out bss */ | 287 | /* zero out bss */ |
271 | lea _edata,%a2 | 288 | lea _edata,%a2 |
272 | lea _end,%a4 | 289 | lea _end,%a4 |
diff --git a/firmware/target/coldfire/i2c-coldfire.c b/firmware/target/coldfire/i2c-coldfire.c index ebfe0a006e..ab3018d713 100644 --- a/firmware/target/coldfire/i2c-coldfire.c +++ b/firmware/target/coldfire/i2c-coldfire.c | |||
@@ -70,6 +70,10 @@ void i2c_init(void) | |||
70 | #elif defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) | 70 | #elif defined(IRIVER_H100_SERIES) || defined(IRIVER_H300_SERIES) |
71 | MBDR = 0; /* iRiver firmware does this */ | 71 | MBDR = 0; /* iRiver firmware does this */ |
72 | MBCR = IEN; /* Enable interface */ | 72 | MBCR = IEN; /* Enable interface */ |
73 | #elif defined(MPIO_HD200) | ||
74 | /* second channel */ | ||
75 | MFDR2 = 0x0d; | ||
76 | MBCR2 = IEN; | ||
73 | #endif | 77 | #endif |
74 | } | 78 | } |
75 | 79 | ||
diff --git a/firmware/target/coldfire/pcm-coldfire.c b/firmware/target/coldfire/pcm-coldfire.c index 0782b116b4..209d227187 100644 --- a/firmware/target/coldfire/pcm-coldfire.c +++ b/firmware/target/coldfire/pcm-coldfire.c | |||
@@ -55,6 +55,24 @@ | |||
55 | 55 | ||
56 | #define FPARM_CLOCKSEL 0 | 56 | #define FPARM_CLOCKSEL 0 |
57 | #define FPARM_CLSEL 1 | 57 | #define FPARM_CLSEL 1 |
58 | |||
59 | /* SCLK = Fs * bit clocks per word | ||
60 | * so SCLK should be Fs * 64 | ||
61 | * | ||
62 | * CLOCKSEL sets SCLK freq based on Audio CLK | ||
63 | * 0x0c SCLK = Audio CLK/2 88200 * 64 = 5644800 Hz | ||
64 | * 0x06 SCLK = Audio CLK/4 44100 * 64 = 2822400 Hz | ||
65 | * 0x04 SCLK = Audio CLK/8 22050 * 64 = 1411200 Hz | ||
66 | * 0x02 SCLK = Audio CLK/16 11025 * 64 = 705600 Hz | ||
67 | * | ||
68 | * CLSEL sets MCLK1/2 DAC freq based on XTAL freq | ||
69 | * 0x01 MCLK1/2 = XTAL freq | ||
70 | * 0x02 MCLK1/2 = XTAL/2 freq | ||
71 | * | ||
72 | * Audio CLK can be XTAL freq or XTAL/2 freq (bit22 in PLLCR) | ||
73 | * we always set bit22 so Audio CLK is always XTAL freq | ||
74 | */ | ||
75 | |||
58 | #if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380) | 76 | #if CONFIG_CPU == MCF5249 && defined(HAVE_UDA1380) |
59 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = | 77 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = |
60 | { | 78 | { |
@@ -65,6 +83,16 @@ static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = | |||
65 | }; | 83 | }; |
66 | #endif | 84 | #endif |
67 | 85 | ||
86 | #if CONFIG_CPU == MCF5249 && defined(HAVE_WM8750) | ||
87 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = | ||
88 | { | ||
89 | [HW_FREQ_88] = { 0x0c, 0x01 }, | ||
90 | [HW_FREQ_44] = { 0x06, 0x01 }, | ||
91 | [HW_FREQ_22] = { 0x04, 0x01 }, | ||
92 | [HW_FREQ_11] = { 0x02, 0x01 }, | ||
93 | }; | ||
94 | #endif | ||
95 | |||
68 | #if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320) | 96 | #if (CONFIG_CPU == MCF5250 || CONFIG_CPU == MCF5249) && defined(HAVE_TLV320) |
69 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = | 97 | static const unsigned char pcm_freq_parms[HW_NUM_FREQ][2] = |
70 | { | 98 | { |
@@ -324,6 +352,7 @@ const void * pcm_play_dma_get_peak_buffer(int *count) | |||
324 | return (void *)((addr + 2) & ~3); | 352 | return (void *)((addr + 2) & ~3); |
325 | } /* pcm_play_dma_get_peak_buffer */ | 353 | } /* pcm_play_dma_get_peak_buffer */ |
326 | 354 | ||
355 | #ifdef HAVE_RECORDING | ||
327 | /**************************************************************************** | 356 | /**************************************************************************** |
328 | ** Recording DMA transfer | 357 | ** Recording DMA transfer |
329 | **/ | 358 | **/ |
@@ -487,3 +516,4 @@ const void * pcm_rec_dma_get_peak_buffer(int *count) | |||
487 | *count = (end >> 2) - addr; | 516 | *count = (end >> 2) - addr; |
488 | return (void *)(addr << 2); | 517 | return (void *)(addr << 2); |
489 | } /* pcm_rec_dma_get_peak_buffer */ | 518 | } /* pcm_rec_dma_get_peak_buffer */ |
519 | #endif | ||
diff --git a/firmware/target/coldfire/system-coldfire.c b/firmware/target/coldfire/system-coldfire.c index a387824526..ba67daa3a6 100644 --- a/firmware/target/coldfire/system-coldfire.c +++ b/firmware/target/coldfire/system-coldfire.c | |||
@@ -152,6 +152,11 @@ default_interrupt (ADC); /* A/D converter */ | |||
152 | #define EXCP_BUTTON_MASK 0x00000202 | 152 | #define EXCP_BUTTON_MASK 0x00000202 |
153 | #define EXCP_BUTTON_VALUE 0x00000200 /* On button and !hold */ | 153 | #define EXCP_BUTTON_VALUE 0x00000200 /* On button and !hold */ |
154 | #define EXCP_PLLCR 0x10800000 | 154 | #define EXCP_PLLCR 0x10800000 |
155 | #elif defined(MPIO_HD200) | ||
156 | #define EXCP_BUTTON_GPIO_READ GPIO1_READ | ||
157 | #define EXCP_BUTTON_MASK 0x01000010 | ||
158 | #define EXCP_BUTTON_VALUE 0x01000000 /* Play button and !hold */ | ||
159 | #define EXCP_PLLCR 0x10800000 | ||
155 | #else | 160 | #else |
156 | #define EXCP_BUTTON_GPIO_READ GPIO1_READ | 161 | #define EXCP_BUTTON_GPIO_READ GPIO1_READ |
157 | #define EXCP_BUTTON_MASK 0x00000022 | 162 | #define EXCP_BUTTON_MASK 0x00000022 |