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author | Nicolas Pennequin <nicolas.pennequin@free.fr> | 2008-05-05 10:32:46 +0000 |
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committer | Nicolas Pennequin <nicolas.pennequin@free.fr> | 2008-05-05 10:32:46 +0000 |
commit | 357ffb3c46a6c371fd84b56acd6f69cb6aad9bb8 (patch) | |
tree | 29035132e1313259010b945c7e37595939d369d9 /firmware/target/coldfire/iaudio/m3/adc-m3.c | |
parent | ef5fa8eaf541a19ccf953051f119e4f56cf3c445 (diff) | |
download | rockbox-357ffb3c46a6c371fd84b56acd6f69cb6aad9bb8.tar.gz rockbox-357ffb3c46a6c371fd84b56acd6f69cb6aad9bb8.zip |
Convert the whole codebase to UTF-8, except docs/COMMITTERS and tools/creative.c, which need checking.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17369 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iaudio/m3/adc-m3.c')
-rw-r--r-- | firmware/target/coldfire/iaudio/m3/adc-m3.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/firmware/target/coldfire/iaudio/m3/adc-m3.c b/firmware/target/coldfire/iaudio/m3/adc-m3.c index 5997f2419a..9f5bf04a64 100644 --- a/firmware/target/coldfire/iaudio/m3/adc-m3.c +++ b/firmware/target/coldfire/iaudio/m3/adc-m3.c | |||
@@ -25,8 +25,8 @@ | |||
25 | 25 | ||
26 | #define ADC_I2C_ADDR 0xa0 | 26 | #define ADC_I2C_ADDR 0xa0 |
27 | 27 | ||
28 | /* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires | 28 | /* The M3 ADC is hooked exclusively to the secondary I²C bus, and requires |
29 | * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read | 29 | * very slow transfers (I²C clock <= 16kHz). So we start one 4-byte read |
30 | * transfer each tick, and handle it via an ISR. At 11MHz, one transfer | 30 | * transfer each tick, and handle it via an ISR. At 11MHz, one transfer |
31 | * takes too long to be started every tick, but it seems we have to live | 31 | * takes too long to be started every tick, but it seems we have to live |
32 | * with that. */ | 32 | * with that. */ |
@@ -92,7 +92,7 @@ unsigned short adc_read(int channel) | |||
92 | 92 | ||
93 | void adc_init(void) | 93 | void adc_init(void) |
94 | { | 94 | { |
95 | MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */ | 95 | MFDR2 = 0x1f; /* I²C clock = SYSCLK / 3840 */ |
96 | MBCR2 = IEN; /* Enable interface */ | 96 | MBCR2 = IEN; /* Enable interface */ |
97 | MBSR2 = 0; /* Clear flags */ | 97 | MBSR2 = 0; /* Clear flags */ |
98 | MBCR2 = (IEN|IIEN); /* Enable interrupts */ | 98 | MBCR2 = (IEN|IIEN); /* Enable interrupts */ |
@@ -105,7 +105,7 @@ void adc_init(void) | |||
105 | sleep(1); /* Ensure valid readings when adc_init returns */ | 105 | sleep(1); /* Ensure valid readings when adc_init returns */ |
106 | } | 106 | } |
107 | 107 | ||
108 | /* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C | 108 | /* The ADC (most probably the PIC12F675) obviously has a slow and buggy I²C |
109 | * implementation. If a transfer is stopped prematurely, it often locks up | 109 | * implementation. If a transfer is stopped prematurely, it often locks up |
110 | * and doesn't react anymore until the unit is power cycled. */ | 110 | * and doesn't react anymore until the unit is power cycled. */ |
111 | 111 | ||