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author | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-03 17:10:44 +0000 |
---|---|---|
committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-04-03 17:10:44 +0000 |
commit | e1a1df69fc5c77bf57c5bb51ca5a084070886872 (patch) | |
tree | b0728426f7109d36e5cc30df33b4754712611764 /firmware/target/arm | |
parent | 27f29904eccceee1725b4dd1d004748f76531e0a (diff) | |
download | rockbox-e1a1df69fc5c77bf57c5bb51ca5a084070886872.tar.gz rockbox-e1a1df69fc5c77bf57c5bb51ca5a084070886872.zip |
Clipv2: fix grey lcd output
We can write to DBOP_DOUT in 8 bits mode : bits 7..0 are mapped to the
LCD, not bits 15..12 and 3..0 like on Clipv1
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25455 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipv2/lcd-as-clipv2.S | 106 | ||||
-rw-r--r-- | firmware/target/arm/as3525/sansa-clipv2/lcd-clipv2.c | 6 |
2 files changed, 108 insertions, 4 deletions
diff --git a/firmware/target/arm/as3525/sansa-clipv2/lcd-as-clipv2.S b/firmware/target/arm/as3525/sansa-clipv2/lcd-as-clipv2.S new file mode 100644 index 0000000000..4281519491 --- /dev/null +++ b/firmware/target/arm/as3525/sansa-clipv2/lcd-as-clipv2.S | |||
@@ -0,0 +1,106 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2008 by Jens Arnold | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "as3525v2.h" | ||
23 | |||
24 | .text | ||
25 | .align 2 | ||
26 | |||
27 | .global lcd_grey_data | ||
28 | .type lcd_grey_data,%function | ||
29 | |||
30 | /* A high performance function to write grey phase data to the display, | ||
31 | * one or multiple pixels. | ||
32 | * | ||
33 | * Arguments: | ||
34 | * r0 - pixel value data address | ||
35 | * r1 - pixel phase data address | ||
36 | * r2 - pixel block count | ||
37 | * | ||
38 | * Register usage: | ||
39 | * r3/r4 - current block of phases | ||
40 | * r5/r6 - current block of values | ||
41 | * r7 - lcd data accumulator | ||
42 | * r12 - phase signs mask | ||
43 | * lr - lcd bridge address | ||
44 | */ | ||
45 | |||
46 | lcd_grey_data: | ||
47 | stmfd sp!, {r4-r7, lr} | ||
48 | mov r12, #0x80 | ||
49 | orr r12, r12, r12, lsl #8 | ||
50 | orr r12, r12, r12, lsl #16 | ||
51 | |||
52 | ldr lr, =GPIOB_BASE | ||
53 | mov r3, #(1<<2) | ||
54 | str r3, [lr, #(4*(1<<2))] @ set pin D/C# of LCD controller (data) | ||
55 | |||
56 | ldr lr, =DBOP_BASE | ||
57 | |||
58 | .greyloop: | ||
59 | ldmia r1, {r3-r4} /* Fetch 8 pixel phases */ | ||
60 | ldmia r0!, {r5-r6} /* Fetch 8 pixel values */ | ||
61 | |||
62 | mov r7, #0 | ||
63 | |||
64 | /* set bits 7..3 */ | ||
65 | tst r3, #0x80 | ||
66 | orrne r7, r7, #0x80 | ||
67 | tst r3, #0x8000 | ||
68 | orrne r7, r7, #0x40 | ||
69 | tst r3, #0x800000 | ||
70 | orrne r7, r7, #0x20 | ||
71 | tst r3, #0x80000000 | ||
72 | orrne r7, r7, #0x10 | ||
73 | bic r3, r3, r12 | ||
74 | add r3, r3, r5 | ||
75 | |||
76 | /* set bits 3..0 */ | ||
77 | tst r4, #0x80 | ||
78 | orrne r7, r7, #0x08 | ||
79 | tst r4, #0x8000 | ||
80 | orrne r7, r7, #0x04 | ||
81 | tst r4, #0x800000 | ||
82 | orrne r7, r7, #0x02 | ||
83 | tst r4, #0x80000000 | ||
84 | orrne r7, r7, #0x01 | ||
85 | bic r4, r4, r12 | ||
86 | add r4, r4, r6 | ||
87 | |||
88 | stmia r1!, {r3-r4} | ||
89 | |||
90 | strb r7, [lr, #0x10] @ DBOP_DOUT | ||
91 | |||
92 | 1: | ||
93 | ldr r5, [lr, #0xC] @ DBOP_STAT | ||
94 | ands r5, r5, #(1<<6) @ wait until push fifo is full | ||
95 | bne 1b | ||
96 | |||
97 | subs r2, r2, #1 | ||
98 | bne .greyloop | ||
99 | |||
100 | 1: | ||
101 | ldr r5, [lr, #0xC] @ DBOP_STAT | ||
102 | ands r5, r5, #(1<<10) @ wait until push fifo empties | ||
103 | beq 1b | ||
104 | |||
105 | ldmfd sp!, {r4-r7, pc} | ||
106 | .size lcd_grey_data,.-lcd_grey_data | ||
diff --git a/firmware/target/arm/as3525/sansa-clipv2/lcd-clipv2.c b/firmware/target/arm/as3525/sansa-clipv2/lcd-clipv2.c index e405036b63..6a8e09a2de 100644 --- a/firmware/target/arm/as3525/sansa-clipv2/lcd-clipv2.c +++ b/firmware/target/arm/as3525/sansa-clipv2/lcd-clipv2.c | |||
@@ -51,8 +51,7 @@ void lcd_write_command(int byte) | |||
51 | DBOP_TIMPOL_23 = 0xE0370036; | 51 | DBOP_TIMPOL_23 = 0xE0370036; |
52 | 52 | ||
53 | /* Write command */ | 53 | /* Write command */ |
54 | /* Only bits 15:12 and 3:0 of DBOP_DOUT are meaningful */ | 54 | DBOP_DOUT8 = byte; |
55 | DBOP_DOUT = (byte << 8) | byte; | ||
56 | 55 | ||
57 | /* While push fifo is not empty */ | 56 | /* While push fifo is not empty */ |
58 | while ((DBOP_STAT & (1<<10)) == 0) | 57 | while ((DBOP_STAT & (1<<10)) == 0) |
@@ -72,8 +71,7 @@ void lcd_write_data(const fb_data* p_bytes, int count) | |||
72 | while (count--) | 71 | while (count--) |
73 | { | 72 | { |
74 | /* Write pixels */ | 73 | /* Write pixels */ |
75 | /* Only bits 15:12 and 3:0 of DBOP_DOUT are meaningful */ | 74 | DBOP_DOUT8 = *p_bytes; |
76 | DBOP_DOUT = (*p_bytes << 8) | *p_bytes; | ||
77 | 75 | ||
78 | p_bytes++; /* next packed pixels */ | 76 | p_bytes++; /* next packed pixels */ |
79 | 77 | ||