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author | Marcoen Hirschberg <marcoen@gmail.com> | 2007-01-17 18:15:50 +0000 |
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committer | Marcoen Hirschberg <marcoen@gmail.com> | 2007-01-17 18:15:50 +0000 |
commit | c64684887ab49749326e2bab61df431a35ed7272 (patch) | |
tree | a0b00e5de218523a389195dc994222d4575ebe20 /firmware/target/arm | |
parent | 020dbcd1cf035cf6978db155b8a746732bcc44b3 (diff) | |
download | rockbox-c64684887ab49749326e2bab61df431a35ed7272.tar.gz rockbox-c64684887ab49749326e2bab61df431a35ed7272.zip |
re-enable CPU scaling (between 100 and 300MHz again) with a new implementation
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12047 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c index ca73b38eed..b7e59e66ea 100644 --- a/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c +++ b/firmware/target/arm/gigabeat/meg-fx/system-meg-fx.c | |||
@@ -75,22 +75,20 @@ void set_cpu_frequency(long frequency) | |||
75 | { | 75 | { |
76 | if (frequency == CPUFREQ_MAX) | 76 | if (frequency == CPUFREQ_MAX) |
77 | { | 77 | { |
78 | /* FCLK: 300MHz, HCLK: 100MHz, PCLK: 50MHz */ | 78 | asm volatile("mov r0, #0\n" |
79 | /* MDIV: 97, PDIV: 1, SDIV: 2 */ | 79 | "mrc p15, 0, r0, c1, c0, 0\n" |
80 | /* HDIV: 3, PDIV: 1 */ | 80 | "orr r0, r0, #3<<30\n" /* set to Asynchronous mode*/ |
81 | "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); | ||
81 | 82 | ||
82 | MPLLCON = (97 << 12) | (1 << 4) | 2; | ||
83 | CLKDIVN = (3 << 1) | 1; | ||
84 | FREQ = CPUFREQ_MAX; | 83 | FREQ = CPUFREQ_MAX; |
85 | } | 84 | } |
86 | else | 85 | else |
87 | { | 86 | { |
88 | /* FCLK: 200MHz, HCLK: 100MHz, PCLK: 50MHz */ | 87 | asm volatile("mov r0, #0\n" |
89 | /* MDIV: 62, PDIV: 1, SDIV: 2 */ | 88 | "mrc p15, 0, r0, c1, c0, 0\n" |
90 | /* HDIV: 1, PDIV: 1 */ | 89 | "bic r0, r0, #3<<30\n" /* set to FastBus mode*/ |
90 | "mcr p15, 0, r0, c1, c0, 0" : : : "r0"); | ||
91 | 91 | ||
92 | MPLLCON = (62 << 12) | (1 << 4) | 2; | ||
93 | CLKDIVN = (1 << 1) | 1; | ||
94 | FREQ = CPUFREQ_NORMAL; | 92 | FREQ = CPUFREQ_NORMAL; |
95 | } | 93 | } |
96 | } | 94 | } |