Use STORAGE_WANTS_ALIGN to make clear it's not a strict necessity

Define PROC_NEEDS_CACHEALIGN only for PP

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25339 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 2 insertions, 4 deletions

diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h
index c531344b64..5f91032d9e 100644
--- a/firmware/target/arm/s5l8700/system-target.h
+++ b/firmware/target/arm/s5l8700/system-target.h
@@ -29,10 +29,8 @@
 #define CPUFREQ_NORMAL  47923200
 #define CPUFREQ_MAX    191692800
 
-/* DMA engine needs aligned addresses */
-#define PROC_NEEDS_CACHEALIGN
 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
-#define NEEDS_STORAGE_ALIGN
+#define WANTS_STORAGE_ALIGN
 
 #define inl(a) (*(volatile unsigned long *) (a))
 #define outl(a,b) (*(volatile unsigned long *) (b) = (a))
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h
index 1422e6467a..157a450743 100644
--- a/firmware/target/arm/system-target.h
+++ b/firmware/target/arm/system-target.h
@@ -164,7 +164,7 @@ static inline void wake_core(int core)
 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
 
 #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
-#define NEEDS_STORAGE_ALIGN
+#define STORAGE_WANTS_ALIGN
 #endif
 
 /** cache functions **/