diff options
author | Barry Wardell <rockbox@barrywardell.net> | 2007-07-31 21:13:35 +0000 |
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committer | Barry Wardell <rockbox@barrywardell.net> | 2007-07-31 21:13:35 +0000 |
commit | ab88fb3738a236fdb106cbb1f60852ff20d07263 (patch) | |
tree | 252d8e2daeb127ea3ed86e97aaa58263c6785335 /firmware/target/arm | |
parent | 2fc19497fc4c72ed02189d9f09f4821bcf7fef1e (diff) | |
download | rockbox-ab88fb3738a236fdb106cbb1f60852ff20d07263.tar.gz rockbox-ab88fb3738a236fdb106cbb1f60852ff20d07263.zip |
Simplify PP502x clock handling code. The code is almost identical between PP502x models, so combine it where possible. Binaries produces are unchanged.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14107 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm')
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 46 |
1 files changed, 11 insertions, 35 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index 7b6ef486cd..c723f1b495 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -122,61 +122,38 @@ static void pp_set_cpu_frequency(long frequency) | |||
122 | 122 | ||
123 | switch (frequency) | 123 | switch (frequency) |
124 | { | 124 | { |
125 | #if CONFIG_CPU == PP5020 | 125 | /* Note: The PP5022 PLL must be run at >= 96MHz |
126 | * Bits 20..21 select the post divider (1/2/4/8). | ||
127 | * PP5026 is similar to PP5022 except it doesn't | ||
128 | * have this limitation (and the post divider?) */ | ||
126 | case CPUFREQ_MAX: | 129 | case CPUFREQ_MAX: |
127 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | 130 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
128 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | 131 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ |
129 | DEV_TIMING1 = 0x00000808; | 132 | DEV_TIMING1 = 0x00000808; |
133 | #if CONFIG_CPU == PP5020 | ||
130 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ | 134 | PLL_CONTROL = 0x8a020a03; /* 10/3 * 24MHz */ |
131 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ | 135 | PLL_STATUS = 0xd19b; /* unlock frequencies > 66MHz */ |
132 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ | 136 | PLL_CONTROL = 0x8a020a03; /* repeat setup */ |
133 | udelay(500); /* wait for relock */ | 137 | udelay(500); /* wait for relock */ |
134 | break; | ||
135 | |||
136 | case CPUFREQ_NORMAL: | ||
137 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | ||
138 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
139 | DEV_TIMING1 = 0x00000303; | ||
140 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ | ||
141 | udelay(500); /* wait for relock */ | ||
142 | break; | ||
143 | |||
144 | case CPUFREQ_SLEEP: | ||
145 | CLOCK_SOURCE = 0x10002202; /* source #2: 32kHz, #1, #3, #4: 24MHz */ | ||
146 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
147 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
148 | udelay(10000); /* let 32kHz source stabilize? */ | ||
149 | break; | ||
150 | |||
151 | default: | ||
152 | CLOCK_SOURCE = 0x10002222; /* source #1, #2, #3, #4: 24MHz */ | ||
153 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
154 | DEV_TIMING1 = 0x00000303; | ||
155 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | ||
156 | cpu_frequency = CPUFREQ_DEFAULT; | ||
157 | break; | ||
158 | |||
159 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | 138 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) |
160 | /* Note: The PP5022 PLL must be run at >= 96MHz | ||
161 | * Bits 20..21 select the post divider (1/2/4/8). | ||
162 | * PP5026 is similar to PP5022 except it doesn't | ||
163 | * have this limitation (and the post divider?) */ | ||
164 | case CPUFREQ_MAX: | ||
165 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | ||
166 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | ||
167 | DEV_TIMING1 = 0x00000808; | ||
168 | PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */ | 139 | PLL_CONTROL = 0x8a121403; /* (20/3 * 24MHz) / 2 */ |
169 | udelay(250); | 140 | udelay(250); |
170 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | 141 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ |
142 | #endif | ||
171 | break; | 143 | break; |
172 | 144 | ||
173 | case CPUFREQ_NORMAL: | 145 | case CPUFREQ_NORMAL: |
174 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ | 146 | CLOCK_SOURCE = 0x10007772; /* source #1: 24MHz, #2, #3, #4: PLL */ |
175 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ | 147 | CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */ |
176 | DEV_TIMING1 = 0x00000303; | 148 | DEV_TIMING1 = 0x00000303; |
149 | #if CONFIG_CPU == PP5020 | ||
150 | PLL_CONTROL = 0x8a020504; /* 5/4 * 24MHz */ | ||
151 | udelay(500); /* wait for relock */ | ||
152 | #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024) | ||
177 | PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */ | 153 | PLL_CONTROL = 0x8a220501; /* (5/1 * 24MHz) / 4 */ |
178 | udelay(250); | 154 | udelay(250); |
179 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ | 155 | while (!(PLL_STATUS & 0x80000000)); /* wait for relock */ |
156 | #endif | ||
180 | break; | 157 | break; |
181 | 158 | ||
182 | case CPUFREQ_SLEEP: | 159 | case CPUFREQ_SLEEP: |
@@ -193,7 +170,6 @@ static void pp_set_cpu_frequency(long frequency) | |||
193 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ | 170 | PLL_CONTROL &= ~0x80000000; /* disable PLL */ |
194 | cpu_frequency = CPUFREQ_DEFAULT; | 171 | cpu_frequency = CPUFREQ_DEFAULT; |
195 | break; | 172 | break; |
196 | #endif | ||
197 | } | 173 | } |
198 | CLOCK_SOURCE = (CLOCK_SOURCE&~0xf000000)|0x20000000; /* select source #2 */ | 174 | CLOCK_SOURCE = (CLOCK_SOURCE&~0xf000000)|0x20000000; /* select source #2 */ |
199 | 175 | ||