Simplify PP502x clock handling code. The code is almost identical between PP502x models, so combine it where possible. Binaries produces are unchanged.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14107 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 11 insertions, 35 deletions

diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c
index 7b6ef486cd..c723f1b495 100644
--- a/firmware/target/arm/system-pp502x.c
+++ b/firmware/target/arm/system-pp502x.c
@@ -122,61 +122,38 @@ static void pp_set_cpu_frequency(long frequency)
 
     switch (frequency)
     {
-#if CONFIG_CPU == PP5020
+      /* Note: The PP5022 PLL must be run at >= 96MHz
+       * Bits 20..21 select the post divider (1/2/4/8).
+       * PP5026 is similar to PP5022 except it doesn't
+       * have this limitation (and the post divider?) */
       case CPUFREQ_MAX:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
         DEV_TIMING1  = 0x00000808;
+#if CONFIG_CPU == PP5020
         PLL_CONTROL  = 0x8a020a03;  /* 10/3 * 24MHz */
         PLL_STATUS   = 0xd19b;      /* unlock frequencies > 66MHz */
         PLL_CONTROL  = 0x8a020a03;  /* repeat setup */
         udelay(500);                /* wait for relock */
-        break;
-
-      case CPUFREQ_NORMAL:
-        CLOCK_SOURCE = 0x10007772;   /* source #1: 24MHz, #2, #3, #4: PLL */
-        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
-        DEV_TIMING1  = 0x00000303;
-        PLL_CONTROL  = 0x8a020504;  /* 5/4 * 24MHz */
-        udelay(500);                /* wait for relock */
-        break;
-
-      case CPUFREQ_SLEEP:
-        CLOCK_SOURCE = 0x10002202;  /* source #2: 32kHz, #1, #3, #4: 24MHz */
-        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
-        PLL_CONTROL &= ~0x80000000; /* disable PLL */
-        udelay(10000);              /* let 32kHz source stabilize? */
-        break;
-
-      default:
-        CLOCK_SOURCE = 0x10002222;  /* source #1, #2, #3, #4: 24MHz */
-        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
-        DEV_TIMING1  = 0x00000303;
-        PLL_CONTROL &= ~0x80000000; /* disable PLL */
-        cpu_frequency = CPUFREQ_DEFAULT;
-        break;
-
 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
-      /* Note: The PP5022 PLL must be run at >= 96MHz
-       * Bits 20..21 select the post divider (1/2/4/8).
-       * PP5026 is similar to PP5022 except it doesn't
-       * have this limitation (and the post divider?) */
-      case CPUFREQ_MAX:
-        CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
-        CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
-        DEV_TIMING1  = 0x00000808;
         PLL_CONTROL  = 0x8a121403;  /* (20/3 * 24MHz) / 2 */
         udelay(250);
         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
+#endif
         break;
 
       case CPUFREQ_NORMAL:
         CLOCK_SOURCE = 0x10007772;  /* source #1: 24MHz, #2, #3, #4: PLL */
         CLCD_CLOCK_SRC &= ~0xc0000000; /* select 24MHz as color LCD clock source */
         DEV_TIMING1  = 0x00000303;
+#if CONFIG_CPU == PP5020
+        PLL_CONTROL  = 0x8a020504;  /* 5/4 * 24MHz */
+        udelay(500);                /* wait for relock */
+#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
         PLL_CONTROL  = 0x8a220501;  /* (5/1 * 24MHz) / 4 */
         udelay(250);
         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
+#endif
         break;
 
       case CPUFREQ_SLEEP:
@@ -193,7 +170,6 @@ static void pp_set_cpu_frequency(long frequency)
         PLL_CONTROL &= ~0x80000000; /* disable PLL */
         cpu_frequency = CPUFREQ_DEFAULT;
         break;
-#endif
     }
     CLOCK_SOURCE = (CLOCK_SOURCE&~0xf000000)|0x20000000;  /* select source #2 */