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authorJens Arnold <amiconn@rockbox.org>2007-07-02 05:16:40 +0000
committerJens Arnold <amiconn@rockbox.org>2007-07-02 05:16:40 +0000
commitfe23dc8f15e9d01ea634d10b334984f1d8760007 (patch)
tree5e12734e3f510c393ca272048f5425435ea26bf3 /firmware/target/arm/wmcodec-pp.c
parent36de1a4d084da18af22d47a435a4eebcf3c50fb2 (diff)
downloadrockbox-fe23dc8f15e9d01ea634d10b334984f1d8760007.tar.gz
rockbox-fe23dc8f15e9d01ea634d10b334984f1d8760007.zip
Improved CPU clock setup for PP502x. PP5020 and PP5022 are not register compatible here, so define the PP5022 targets properly, and introduce a CPU_PP502x macro for easier family check. Improves stability on PP5020 (less freezing, tested with Mini G1) and reduces clock change penalty (500us on PP5020; uses the relock bit on PP5022).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13763 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/wmcodec-pp.c')
-rw-r--r--firmware/target/arm/wmcodec-pp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/wmcodec-pp.c b/firmware/target/arm/wmcodec-pp.c
index 505a31deb4..7d00369bf0 100644
--- a/firmware/target/arm/wmcodec-pp.c
+++ b/firmware/target/arm/wmcodec-pp.c
@@ -43,7 +43,7 @@ int audiohw_init(void) {
43 /* reset I2C */ 43 /* reset I2C */
44 i2c_init(); 44 i2c_init();
45 45
46#if CONFIG_CPU == PP5020 46#ifdef CPU_PP502x
47 /* normal outputs for CDI and I2S pin groups */ 47 /* normal outputs for CDI and I2S pin groups */
48 DEV_INIT &= ~0x300; 48 DEV_INIT &= ~0x300;
49 49