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author | Karl Kurbjun <kkurbjun@gmail.com> | 2009-04-01 03:21:18 +0000 |
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committer | Karl Kurbjun <kkurbjun@gmail.com> | 2009-04-01 03:21:18 +0000 |
commit | 4fa96fbc914ae8fd69aedafd73f4f1798679d29f (patch) | |
tree | ea0deb3e1573e1dfd540441002e58b403670d178 /firmware/target/arm/tms320dm320/crt0.S | |
parent | a606121dd860245328198ac773d454980191abc3 (diff) | |
download | rockbox-4fa96fbc914ae8fd69aedafd73f4f1798679d29f.tar.gz rockbox-4fa96fbc914ae8fd69aedafd73f4f1798679d29f.zip |
M:Robe 500i: More LCD initialization, and beginnings of support for QVGA as well as VGA on the LCD. MPEGPlayer now works with reasonable performance on smaller videos, but YUV blitting persists after MPEGPlayer is left, some cleanup/changes to the initialization code. This should be functionally equivalent for the ZVM, but the #ifdef's may need to be added back for app.lds. Get the bootloader building again.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20598 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/tms320dm320/crt0.S')
-rwxr-xr-x | firmware/target/arm/tms320dm320/crt0.S | 105 |
1 files changed, 24 insertions, 81 deletions
diff --git a/firmware/target/arm/tms320dm320/crt0.S b/firmware/target/arm/tms320dm320/crt0.S index 9375de7d0d..a5a965b9c2 100755 --- a/firmware/target/arm/tms320dm320/crt0.S +++ b/firmware/target/arm/tms320dm320/crt0.S | |||
@@ -30,20 +30,6 @@ | |||
30 | 30 | ||
31 | .global start | 31 | .global start |
32 | start: | 32 | start: |
33 | .equ INTC_IRQ0, 0x00030508 | ||
34 | .equ INTC_IRQ1, 0x0003050A | ||
35 | .equ INTC_IRQ2, 0x0003050C | ||
36 | .equ INTC_FIQ0, 0x00030500 | ||
37 | .equ INTC_FIQ1, 0x00030502 | ||
38 | .equ INTC_FIQ2, 0x00030504 | ||
39 | .equ INTC_EINT0, 0x00030528 | ||
40 | .equ INTC_EINT1, 0x0003052A | ||
41 | .equ INTC_EINT2, 0x0003052C | ||
42 | .equ INTC_FISEL0, 0x00030520 | ||
43 | .equ INTC_FISEL1, 0x00030522 | ||
44 | .equ INTC_FISEL2, 0x00030524 | ||
45 | .equ INTC_MASK, 0xFFFFFFFF | ||
46 | |||
47 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ | 33 | msr cpsr, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */ |
48 | 34 | ||
49 | #ifndef CREATIVE_ZVx | 35 | #ifndef CREATIVE_ZVx |
@@ -68,37 +54,6 @@ start: | |||
68 | orr r0, r0, #0x00000002 | 54 | orr r0, r0, #0x00000002 |
69 | mcr p15, 0, r0, c1, c0, 0 | 55 | mcr p15, 0, r0, c1, c0, 0 |
70 | 56 | ||
71 | #if 0 | ||
72 | /* mask interrupts */ | ||
73 | ldr r1, =INTC_MASK | ||
74 | ldr r2, =INTC_IRQ0 | ||
75 | strh r1, [r2] | ||
76 | ldr r2, =INTC_IRQ1 | ||
77 | strh r1, [r2] | ||
78 | ldr r2, =INTC_IRQ2 | ||
79 | strh r1, [r2] | ||
80 | ldr r2, =INTC_FIQ0 | ||
81 | strh r1, [r2] | ||
82 | ldr r2, =INTC_FIQ1 | ||
83 | strh r1, [r2] | ||
84 | ldr r2, =INTC_FIQ2 | ||
85 | strh r1, [r2] | ||
86 | |||
87 | mov r1, #0 | ||
88 | ldr r2, =INTC_EINT0 | ||
89 | strh r1, [r2] | ||
90 | ldr r2, =INTC_EINT1 | ||
91 | strh r1, [r2] | ||
92 | ldr r2, =INTC_EINT2 | ||
93 | strh r1, [r2] | ||
94 | ldr r2, =INTC_FISEL0 | ||
95 | strh r1, [r2] | ||
96 | ldr r2, =INTC_FISEL1 | ||
97 | strh r1, [r2] | ||
98 | ldr r2, =INTC_FISEL2 | ||
99 | strh r1, [r2] | ||
100 | #endif | ||
101 | |||
102 | #if !defined(BOOTLOADER) && !defined(STUB) | 57 | #if !defined(BOOTLOADER) && !defined(STUB) |
103 | /* Zero out IBSS */ | 58 | /* Zero out IBSS */ |
104 | ldr r2, =_iedata | 59 | ldr r2, =_iedata |
@@ -122,25 +77,25 @@ start: | |||
122 | #endif | 77 | #endif |
123 | #endif /* !BOOTLOADER,!STUB */ | 78 | #endif /* !BOOTLOADER,!STUB */ |
124 | 79 | ||
125 | /* Initialise bss section to zero */ | ||
126 | ldr r2, =_edata | ||
127 | ldr r3, =_end | ||
128 | mov r4, #0 | ||
129 | 1: | ||
130 | cmp r3, r2 | ||
131 | strhi r4, [r2], #4 | ||
132 | bhi 1b | ||
133 | 80 | ||
134 | /* Load stack munge value */ | 81 | /* Initialise bss section to zero */ |
135 | ldr r4, =0xdeadbeef | 82 | ldr r2, =_edata |
83 | ldr r3, =_end | ||
84 | mov r4, #0 | ||
85 | bsszero: | ||
86 | cmp r3, r2 | ||
87 | strhi r4, [r2], #4 | ||
88 | bhi bsszero | ||
136 | 89 | ||
137 | /* Set up some stack and munge it with 0xdeadbeef */ | 90 | /* Set up some stack and munge it with 0xdeadbeef */ |
138 | ldr r2, =stackbegin | 91 | ldr sp, =stackend |
139 | ldr r3, =stackend | 92 | mov r3, sp |
140 | 1: | 93 | ldr r2, =stackbegin |
141 | cmp r3, r2 | 94 | ldr r4, =0xdeadbeef |
142 | strhi r4, [r2], #4 | 95 | stackmunge: |
143 | bhi 1b | 96 | cmp r3, r2 |
97 | strhi r4, [r2], #4 | ||
98 | bhi stackmunge | ||
144 | 99 | ||
145 | /* Set up stack for IRQ mode */ | 100 | /* Set up stack for IRQ mode */ |
146 | msr cpsr_c, #0xd2 /* IRQ disabled, FIQ enabled */ | 101 | msr cpsr_c, #0xd2 /* IRQ disabled, FIQ enabled */ |
@@ -185,26 +140,14 @@ start_loc: | |||
185 | 140 | ||
186 | /* Exception handlers. Will be copied to address 0 after memory remapping */ | 141 | /* Exception handlers. Will be copied to address 0 after memory remapping */ |
187 | .section .vectors,"aw" | 142 | .section .vectors,"aw" |
188 | ldr pc, [pc, #24] | 143 | b start |
189 | ldr pc, [pc, #24] | 144 | b undef_instr_handler |
190 | ldr pc, [pc, #24] | 145 | b software_int_handler |
191 | ldr pc, [pc, #24] | 146 | b prefetch_abort_handler |
192 | ldr pc, [pc, #24] | 147 | b data_abort_handler |
193 | ldr pc, [pc, #24] | 148 | b reserved_handler |
194 | ldr pc, [pc, #24] | 149 | b irq_handler |
195 | ldr pc, [pc, #24] | 150 | b fiq_handler |
196 | |||
197 | /* Exception vectors */ | ||
198 | .global vectors | ||
199 | vectors: | ||
200 | .word start | ||
201 | .word undef_instr_handler | ||
202 | .word software_int_handler | ||
203 | .word prefetch_abort_handler | ||
204 | .word data_abort_handler | ||
205 | .word reserved_handler | ||
206 | .word irq_handler | ||
207 | .word fiq_handler | ||
208 | 151 | ||
209 | .text | 152 | .text |
210 | 153 | ||