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authorMichael Sevakis <jethead71@rockbox.org>2013-07-19 08:18:16 -0400
committerMichael Sevakis <jethead71@rockbox.org>2013-07-19 08:18:16 -0400
commitd2249dce6f4dda8cb71e048ced6562f26515d27f (patch)
tree897a1da0147d9ea459d6ca3ec7234695dacfaa49 /firmware/target/arm/tatung
parent4596f51c90db76d125c7c963efa4876443a82440 (diff)
downloadrockbox-d2249dce6f4dda8cb71e048ced6562f26515d27f.tar.gz
rockbox-d2249dce6f4dda8cb71e048ced6562f26515d27f.zip
Combine PortalPlayer .lds files into one for app and boot.
These nearly identical files are multiplying like rabbits as PP targets are added and make SoC-related changes a PITA. Just include the master .lds file from the target one as was done for bootloader USB. Change-Id: I65e9e653030f0688b1728e32ada16abf2932e029
Diffstat (limited to 'firmware/target/arm/tatung')
-rw-r--r--firmware/target/arm/tatung/app.lds184
-rw-r--r--firmware/target/arm/tatung/boot.lds64
2 files changed, 2 insertions, 246 deletions
diff --git a/firmware/target/arm/tatung/app.lds b/firmware/target/arm/tatung/app.lds
index 4752e40ab7..856cc52bb0 100644
--- a/firmware/target/arm/tatung/app.lds
+++ b/firmware/target/arm/tatung/app.lds
@@ -1,184 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92
93 .ibss IRAMORIG (NOLOAD) :
94 {
95 _iedata = .;
96 *(.qharray)
97 *(.ibss)
98 . = ALIGN(0x4);
99 _iend = .;
100 } > IRAM
101
102 .iram _iend :
103 {
104 _iramstart = .;
105 *(.icode)
106 *(.irodata)
107 *(.idata)
108 . = ALIGN(0x4);
109 _iramend = .;
110 } > IRAM AT> DRAM
111
112 _iramcopy = LOADADDR(.iram);
113
114 .idle_stacks (NOLOAD) :
115 {
116 *(.idle_stacks)
117#if NUM_CORES > 1
118 cpu_idlestackbegin = .;
119 . += IDLE_STACK_SIZE;
120 cpu_idlestackend = .;
121#endif
122 cop_idlestackbegin = .;
123 . += IDLE_STACK_SIZE;
124 cop_idlestackend = .;
125 } > IRAM
126
127 .stack (NOLOAD) :
128 {
129 *(.stack)
130 stackbegin = .;
131 . += 0x2000;
132 stackend = .;
133 } > IRAM
134
135 /* .bss and .ncbss are treated as a single section to use one init loop to
136 * zero it - note "_edata" and "_end" */
137 .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
138 SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
139 {
140 _edata = .;
141 *(.bss*)
142 *(COMMON)
143 . = ALIGN(0x4);
144 } > DRAM
145
146#if NOCACHE_BASE != 0
147 .ncbss . + NOCACHE_BASE (NOLOAD):
148 {
149 . = ALIGN(CACHEALIGN_SIZE);
150 *(.ncbss*)
151 . = ALIGN(CACHEALIGN_SIZE);
152 } AT> DRAM
153#endif
154
155 /* This will be aligned by preceding alignments */
156 .endaddr . - NOCACHE_BASE (NOLOAD) :
157 {
158 _end = .;
159 } > DRAM
160
161 .audiobuf (NOLOAD) :
162 {
163 _audiobuffer = .;
164 audiobuffer = .;
165 } > DRAM
166
167 .audiobufend ENDAUDIOADDR (NOLOAD) :
168 {
169 audiobufend = .;
170 _audiobufend = .;
171 } > DRAM
172
173 .codec ENDAUDIOADDR (NOLOAD) :
174 {
175 codecbuf = .;
176 _codecbuf = .;
177 }
178
179 .plugin ENDADDR (NOLOAD) :
180 {
181 _pluginbuf = .;
182 pluginbuf = .;
183 }
184}
diff --git a/firmware/target/arm/tatung/boot.lds b/firmware/target/arm/tatung/boot.lds
index 98d9cb62fe..33b826bec8 100644
--- a/firmware/target/arm/tatung/boot.lds
+++ b/firmware/target/arm/tatung/boot.lds
@@ -1,64 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/boot-pp.lds"
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#define DRAMORIG 0x10000000
11#define IRAMORIG 0x40000000
12#define IRAMSIZE 0x18000
13#define FLASHORIG 0x001f0000
14#define FLASHSIZE 2M
15
16MEMORY
17{
18 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
19 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
20}
21
22SECTIONS
23{
24 . = IRAMORIG;
25
26 .text : {
27 *(.init.text)
28 *(.text*)
29 *(.glue_7)
30 *(.glue_7t)
31 } > IRAM
32
33 .data : {
34 *(.icode)
35 *(.irodata)
36 *(.idata)
37 *(.data*)
38 *(.ncdata*)
39 *(.rodata*)
40 _dataend = . ;
41 } > IRAM
42
43 .stack (NOLOAD) : {
44 *(.stack)
45 _stackbegin = .;
46 stackbegin = .;
47 . += 0x2000;
48 _stackend = .;
49 stackend = .;
50 } > IRAM
51
52 /* The bss section is too large for IRAM - we just move it 16MB into the
53 DRAM */
54
55 . = DRAMORIG;
56 .bss . + (16*1024*1024) (NOLOAD) : {
57 _edata = .;
58 *(.bss*);
59 *(.ibss);
60 *(COMMON)
61 *(.ncbss*);
62 _end = .;
63 } > DRAM
64}