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authorMichael Sevakis <jethead71@rockbox.org>2013-07-19 08:18:16 -0400
committerMichael Sevakis <jethead71@rockbox.org>2013-07-19 08:18:16 -0400
commitd2249dce6f4dda8cb71e048ced6562f26515d27f (patch)
tree897a1da0147d9ea459d6ca3ec7234695dacfaa49 /firmware/target
parent4596f51c90db76d125c7c963efa4876443a82440 (diff)
downloadrockbox-d2249dce6f4dda8cb71e048ced6562f26515d27f.tar.gz
rockbox-d2249dce6f4dda8cb71e048ced6562f26515d27f.zip
Combine PortalPlayer .lds files into one for app and boot.
These nearly identical files are multiplying like rabbits as PP targets are added and make SoC-related changes a PITA. Just include the master .lds file from the target one as was done for bootloader USB. Change-Id: I65e9e653030f0688b1728e32ada16abf2932e029
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/arm/ipod/app.lds200
-rw-r--r--firmware/target/arm/ipod/boot.lds80
-rw-r--r--firmware/target/arm/iriver/app.lds196
-rw-r--r--firmware/target/arm/olympus/app.lds196
-rw-r--r--firmware/target/arm/olympus/boot.lds64
-rw-r--r--firmware/target/arm/pbell/app.lds196
-rw-r--r--firmware/target/arm/pbell/boot.lds64
-rw-r--r--firmware/target/arm/philips/app.lds196
-rw-r--r--firmware/target/arm/philips/boot.lds67
-rw-r--r--firmware/target/arm/pp/app-pp.lds199
-rw-r--r--firmware/target/arm/pp/boot-pp.lds92
-rw-r--r--firmware/target/arm/samsung/app.lds196
-rw-r--r--firmware/target/arm/samsung/boot.lds64
-rw-r--r--firmware/target/arm/sandisk/app.lds193
-rw-r--r--firmware/target/arm/sandisk/boot.lds77
-rw-r--r--firmware/target/arm/tatung/app.lds184
-rw-r--r--firmware/target/arm/tatung/boot.lds64
17 files changed, 308 insertions, 2020 deletions
diff --git a/firmware/target/arm/ipod/app.lds b/firmware/target/arm/ipod/app.lds
index 258f296a85..856cc52bb0 100644
--- a/firmware/target/arm/ipod/app.lds
+++ b/firmware/target/arm/ipod/app.lds
@@ -1,200 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92 _noloaddram = LOADADDR(.vectors);
93
94 .ibss IRAMORIG (NOLOAD) :
95 {
96 _iedata = .;
97 *(.qharray)
98 *(.ibss)
99 . = ALIGN(0x4);
100 _iend = .;
101 } > IRAM
102
103 .iram _iend :
104 {
105 _iramstart = .;
106 *(.icode)
107 *(.irodata)
108 *(.idata)
109 . = ALIGN(0x4);
110 _iramend = .;
111 } > IRAM AT> DRAM
112
113 _iramcopy = LOADADDR(.iram);
114
115
116 .init ENDAUDIOADDR :
117 {
118 . = ALIGN(4);
119 _initstart = .;
120 *(.init*)
121 _initend = .;
122 } AT> DRAM
123
124 _initcopy = LOADADDR(.init);
125
126 .idle_stacks (NOLOAD) :
127 {
128 *(.idle_stacks)
129#if NUM_CORES > 1
130 cpu_idlestackbegin = .;
131 . += IDLE_STACK_SIZE;
132 cpu_idlestackend = .;
133#endif
134 cop_idlestackbegin = .;
135 . += IDLE_STACK_SIZE;
136 cop_idlestackend = .;
137 } > IRAM
138
139 .stack (NOLOAD) :
140 {
141 *(.stack)
142 stackbegin = .;
143 . += 0x2000;
144 stackend = .;
145 } > IRAM
146
147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss _noloaddram (NOLOAD) :
150 {
151 _edata = .;
152 *(.bss*)
153 *(COMMON)
154 . = ALIGN(0x4);
155 } > DRAM
156
157#if NOCACHE_BASE != 0
158 .ncbss . + NOCACHE_BASE (NOLOAD):
159 {
160 . = ALIGN(CACHEALIGN_SIZE);
161 *(.ncbss*)
162 . = ALIGN(CACHEALIGN_SIZE);
163 } AT> DRAM
164#endif
165
166 /* This will be aligned by preceding alignments */
167 .endaddr . - NOCACHE_BASE (NOLOAD) :
168 {
169 _end = .;
170 } > DRAM
171
172 .audiobuf (NOLOAD) :
173 {
174 _audiobuffer = .;
175 . = ALIGN(0x4);
176 audiobuffer = .;
177 } > DRAM
178
179 .audiobufend ENDAUDIOADDR (NOLOAD) :
180 {
181#ifdef IPOD_VIDEO
182 audiobufend_lds = .;
183#else
184 audiobufend = .;
185#endif
186 _audiobufend = .;
187 } > DRAM
188
189 .codec ENDAUDIOADDR (NOLOAD) :
190 {
191 codecbuf = .;
192 _codecbuf = .;
193 }
194
195 .plugin ENDADDR (NOLOAD) :
196 {
197 _pluginbuf = .;
198 pluginbuf = .;
199 }
200}
diff --git a/firmware/target/arm/ipod/boot.lds b/firmware/target/arm/ipod/boot.lds
index 6cd30c9eee..33b826bec8 100644
--- a/firmware/target/arm/ipod/boot.lds
+++ b/firmware/target/arm/ipod/boot.lds
@@ -1,80 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/boot-pp.lds"
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#if CONFIG_CPU == PP5020
11#define DRAMORIG 0x10000000
12#define IRAMORIG 0x40000000
13#define IRAMSIZE 0x18000
14#define FLASHORIG 0x001f0000
15#define FLASHSIZE 2M
16#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
17#define DRAMORIG 0x10000000
18#ifndef IRAMORIG
19#define IRAMORIG 0x40000000
20#endif
21#define IRAMSIZE 0x20000
22#define FLASHORIG 0x001f0000
23#define FLASHSIZE 2M
24#elif CONFIG_CPU == PP5002
25#define DRAMORIG 0x28000000
26#define IRAMORIG 0x40000000
27#define IRAMSIZE 0x18000
28#define FLASHORIG 0x001f0000
29#define FLASHSIZE 2M
30#endif
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 . = IRAMORIG;
41
42 .text : {
43 *(.init.text)
44 *(.text*)
45 *(.glue_7)
46 *(.glue_7t)
47 } > IRAM
48
49 .data : {
50 *(.icode)
51 *(.irodata)
52 *(.idata)
53 *(.data*)
54 *(.ncdata*)
55 *(.rodata*)
56 _dataend = . ;
57 } > IRAM
58
59 .stack (NOLOAD) : {
60 *(.stack)
61 _stackbegin = .;
62 stackbegin = .;
63 . += 0x2000;
64 _stackend = .;
65 stackend = .;
66 } > IRAM
67
68 /* The bss section is too large for IRAM - we just move it 16MB into the
69 DRAM */
70
71 . = DRAMORIG;
72 .bss . + (16*1024*1024) (NOLOAD) : {
73 _edata = .;
74 *(.bss*);
75 *(.ibss);
76 *(COMMON)
77 *(.ncbss*);
78 _end = .;
79 } > DRAM
80}
diff --git a/firmware/target/arm/iriver/app.lds b/firmware/target/arm/iriver/app.lds
index 30e5962b82..856cc52bb0 100644
--- a/firmware/target/arm/iriver/app.lds
+++ b/firmware/target/arm/iriver/app.lds
@@ -1,196 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92 _noloaddram = LOADADDR(.vectors);
93
94 .ibss IRAMORIG (NOLOAD) :
95 {
96 _iedata = .;
97 *(.qharray)
98 *(.ibss)
99 . = ALIGN(0x4);
100 _iend = .;
101 } > IRAM
102
103 .iram _iend :
104 {
105 _iramstart = .;
106 *(.icode)
107 *(.irodata)
108 *(.idata)
109 . = ALIGN(0x4);
110 _iramend = .;
111 } > IRAM AT> DRAM
112
113 _iramcopy = LOADADDR(.iram);
114
115
116 .init ENDAUDIOADDR :
117 {
118 . = ALIGN(4);
119 _initstart = .;
120 *(.init*)
121 _initend = .;
122 } AT> DRAM
123
124 _initcopy = LOADADDR(.init);
125
126 .idle_stacks (NOLOAD) :
127 {
128 *(.idle_stacks)
129#if NUM_CORES > 1
130 cpu_idlestackbegin = .;
131 . += IDLE_STACK_SIZE;
132 cpu_idlestackend = .;
133#endif
134 cop_idlestackbegin = .;
135 . += IDLE_STACK_SIZE;
136 cop_idlestackend = .;
137 } > IRAM
138
139 .stack (NOLOAD) :
140 {
141 *(.stack)
142 stackbegin = .;
143 . += 0x2000;
144 stackend = .;
145 } > IRAM
146
147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss _noloaddram (NOLOAD) :
150 {
151 _edata = .;
152 *(.bss*)
153 *(COMMON)
154 . = ALIGN(0x4);
155 } > DRAM
156
157#if NOCACHE_BASE != 0
158 .ncbss . + NOCACHE_BASE (NOLOAD):
159 {
160 . = ALIGN(CACHEALIGN_SIZE);
161 *(.ncbss*)
162 . = ALIGN(CACHEALIGN_SIZE);
163 } AT> DRAM
164#endif
165
166 /* This will be aligned by preceding alignments */
167 .endaddr . - NOCACHE_BASE (NOLOAD) :
168 {
169 _end = .;
170 } > DRAM
171
172 .audiobuf (NOLOAD) :
173 {
174 _audiobuffer = .;
175 . = ALIGN(0x4);
176 audiobuffer = .;
177 } > DRAM
178
179 .audiobufend ENDAUDIOADDR (NOLOAD) :
180 {
181 audiobufend = .;
182 _audiobufend = .;
183 } > DRAM
184
185 .codec ENDAUDIOADDR (NOLOAD) :
186 {
187 codecbuf = .;
188 _codecbuf = .;
189 }
190
191 .plugin ENDADDR (NOLOAD) :
192 {
193 _pluginbuf = .;
194 pluginbuf = .;
195 }
196}
diff --git a/firmware/target/arm/olympus/app.lds b/firmware/target/arm/olympus/app.lds
index 30e5962b82..856cc52bb0 100644
--- a/firmware/target/arm/olympus/app.lds
+++ b/firmware/target/arm/olympus/app.lds
@@ -1,196 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92 _noloaddram = LOADADDR(.vectors);
93
94 .ibss IRAMORIG (NOLOAD) :
95 {
96 _iedata = .;
97 *(.qharray)
98 *(.ibss)
99 . = ALIGN(0x4);
100 _iend = .;
101 } > IRAM
102
103 .iram _iend :
104 {
105 _iramstart = .;
106 *(.icode)
107 *(.irodata)
108 *(.idata)
109 . = ALIGN(0x4);
110 _iramend = .;
111 } > IRAM AT> DRAM
112
113 _iramcopy = LOADADDR(.iram);
114
115
116 .init ENDAUDIOADDR :
117 {
118 . = ALIGN(4);
119 _initstart = .;
120 *(.init*)
121 _initend = .;
122 } AT> DRAM
123
124 _initcopy = LOADADDR(.init);
125
126 .idle_stacks (NOLOAD) :
127 {
128 *(.idle_stacks)
129#if NUM_CORES > 1
130 cpu_idlestackbegin = .;
131 . += IDLE_STACK_SIZE;
132 cpu_idlestackend = .;
133#endif
134 cop_idlestackbegin = .;
135 . += IDLE_STACK_SIZE;
136 cop_idlestackend = .;
137 } > IRAM
138
139 .stack (NOLOAD) :
140 {
141 *(.stack)
142 stackbegin = .;
143 . += 0x2000;
144 stackend = .;
145 } > IRAM
146
147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss _noloaddram (NOLOAD) :
150 {
151 _edata = .;
152 *(.bss*)
153 *(COMMON)
154 . = ALIGN(0x4);
155 } > DRAM
156
157#if NOCACHE_BASE != 0
158 .ncbss . + NOCACHE_BASE (NOLOAD):
159 {
160 . = ALIGN(CACHEALIGN_SIZE);
161 *(.ncbss*)
162 . = ALIGN(CACHEALIGN_SIZE);
163 } AT> DRAM
164#endif
165
166 /* This will be aligned by preceding alignments */
167 .endaddr . - NOCACHE_BASE (NOLOAD) :
168 {
169 _end = .;
170 } > DRAM
171
172 .audiobuf (NOLOAD) :
173 {
174 _audiobuffer = .;
175 . = ALIGN(0x4);
176 audiobuffer = .;
177 } > DRAM
178
179 .audiobufend ENDAUDIOADDR (NOLOAD) :
180 {
181 audiobufend = .;
182 _audiobufend = .;
183 } > DRAM
184
185 .codec ENDAUDIOADDR (NOLOAD) :
186 {
187 codecbuf = .;
188 _codecbuf = .;
189 }
190
191 .plugin ENDADDR (NOLOAD) :
192 {
193 _pluginbuf = .;
194 pluginbuf = .;
195 }
196}
diff --git a/firmware/target/arm/olympus/boot.lds b/firmware/target/arm/olympus/boot.lds
index 98d9cb62fe..33b826bec8 100644
--- a/firmware/target/arm/olympus/boot.lds
+++ b/firmware/target/arm/olympus/boot.lds
@@ -1,64 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/boot-pp.lds"
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#define DRAMORIG 0x10000000
11#define IRAMORIG 0x40000000
12#define IRAMSIZE 0x18000
13#define FLASHORIG 0x001f0000
14#define FLASHSIZE 2M
15
16MEMORY
17{
18 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
19 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
20}
21
22SECTIONS
23{
24 . = IRAMORIG;
25
26 .text : {
27 *(.init.text)
28 *(.text*)
29 *(.glue_7)
30 *(.glue_7t)
31 } > IRAM
32
33 .data : {
34 *(.icode)
35 *(.irodata)
36 *(.idata)
37 *(.data*)
38 *(.ncdata*)
39 *(.rodata*)
40 _dataend = . ;
41 } > IRAM
42
43 .stack (NOLOAD) : {
44 *(.stack)
45 _stackbegin = .;
46 stackbegin = .;
47 . += 0x2000;
48 _stackend = .;
49 stackend = .;
50 } > IRAM
51
52 /* The bss section is too large for IRAM - we just move it 16MB into the
53 DRAM */
54
55 . = DRAMORIG;
56 .bss . + (16*1024*1024) (NOLOAD) : {
57 _edata = .;
58 *(.bss*);
59 *(.ibss);
60 *(COMMON)
61 *(.ncbss*);
62 _end = .;
63 } > DRAM
64}
diff --git a/firmware/target/arm/pbell/app.lds b/firmware/target/arm/pbell/app.lds
index 30e5962b82..856cc52bb0 100644
--- a/firmware/target/arm/pbell/app.lds
+++ b/firmware/target/arm/pbell/app.lds
@@ -1,196 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92 _noloaddram = LOADADDR(.vectors);
93
94 .ibss IRAMORIG (NOLOAD) :
95 {
96 _iedata = .;
97 *(.qharray)
98 *(.ibss)
99 . = ALIGN(0x4);
100 _iend = .;
101 } > IRAM
102
103 .iram _iend :
104 {
105 _iramstart = .;
106 *(.icode)
107 *(.irodata)
108 *(.idata)
109 . = ALIGN(0x4);
110 _iramend = .;
111 } > IRAM AT> DRAM
112
113 _iramcopy = LOADADDR(.iram);
114
115
116 .init ENDAUDIOADDR :
117 {
118 . = ALIGN(4);
119 _initstart = .;
120 *(.init*)
121 _initend = .;
122 } AT> DRAM
123
124 _initcopy = LOADADDR(.init);
125
126 .idle_stacks (NOLOAD) :
127 {
128 *(.idle_stacks)
129#if NUM_CORES > 1
130 cpu_idlestackbegin = .;
131 . += IDLE_STACK_SIZE;
132 cpu_idlestackend = .;
133#endif
134 cop_idlestackbegin = .;
135 . += IDLE_STACK_SIZE;
136 cop_idlestackend = .;
137 } > IRAM
138
139 .stack (NOLOAD) :
140 {
141 *(.stack)
142 stackbegin = .;
143 . += 0x2000;
144 stackend = .;
145 } > IRAM
146
147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss _noloaddram (NOLOAD) :
150 {
151 _edata = .;
152 *(.bss*)
153 *(COMMON)
154 . = ALIGN(0x4);
155 } > DRAM
156
157#if NOCACHE_BASE != 0
158 .ncbss . + NOCACHE_BASE (NOLOAD):
159 {
160 . = ALIGN(CACHEALIGN_SIZE);
161 *(.ncbss*)
162 . = ALIGN(CACHEALIGN_SIZE);
163 } AT> DRAM
164#endif
165
166 /* This will be aligned by preceding alignments */
167 .endaddr . - NOCACHE_BASE (NOLOAD) :
168 {
169 _end = .;
170 } > DRAM
171
172 .audiobuf (NOLOAD) :
173 {
174 _audiobuffer = .;
175 . = ALIGN(0x4);
176 audiobuffer = .;
177 } > DRAM
178
179 .audiobufend ENDAUDIOADDR (NOLOAD) :
180 {
181 audiobufend = .;
182 _audiobufend = .;
183 } > DRAM
184
185 .codec ENDAUDIOADDR (NOLOAD) :
186 {
187 codecbuf = .;
188 _codecbuf = .;
189 }
190
191 .plugin ENDADDR (NOLOAD) :
192 {
193 _pluginbuf = .;
194 pluginbuf = .;
195 }
196}
diff --git a/firmware/target/arm/pbell/boot.lds b/firmware/target/arm/pbell/boot.lds
index 9a42569aea..33b826bec8 100644
--- a/firmware/target/arm/pbell/boot.lds
+++ b/firmware/target/arm/pbell/boot.lds
@@ -1,64 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/boot-pp.lds"
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#define DRAMORIG 0x10000000
11#define IRAMORIG 0x40000000
12#define IRAMSIZE 0x18000
13#define FLASHORIG 0x001f0000
14#define FLASHSIZE 2M
15
16MEMORY
17{
18 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
19 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
20}
21
22SECTIONS
23{
24 . = IRAMORIG;
25
26 .text : {
27 *(.init.text)
28 *(.text*)
29 *(.glue_7)
30 *(.glue_7t)
31 } > IRAM
32
33 .data : {
34 *(.icode)
35 *(.irodata)
36 *(.idata)
37 *(.data*)
38 *(.ncdata*)
39 *(.rodata*)
40 _dataend = . ;
41 } > IRAM
42
43 .stack (NOLOAD) : {
44 *(.stack)
45 _stackbegin = .;
46 stackbegin = .;
47 . += 0x2000;
48 _stackend = .;
49 stackend = .;
50 } > IRAM
51
52 /* The bss section is too large for IRAM - we just move it 16MB into the
53 DRAM */
54
55 . = DRAMORIG;
56 .bss . + (16*1024*1024) (NOLOAD) : {
57 _edata = .;
58 *(.bss*);
59 *(.ibss);
60 *(COMMON)
61 *(.ncbss*);
62 _end = .;
63 } > DRAM
64}
diff --git a/firmware/target/arm/philips/app.lds b/firmware/target/arm/philips/app.lds
index 30e5962b82..856cc52bb0 100644
--- a/firmware/target/arm/philips/app.lds
+++ b/firmware/target/arm/philips/app.lds
@@ -1,196 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92 _noloaddram = LOADADDR(.vectors);
93
94 .ibss IRAMORIG (NOLOAD) :
95 {
96 _iedata = .;
97 *(.qharray)
98 *(.ibss)
99 . = ALIGN(0x4);
100 _iend = .;
101 } > IRAM
102
103 .iram _iend :
104 {
105 _iramstart = .;
106 *(.icode)
107 *(.irodata)
108 *(.idata)
109 . = ALIGN(0x4);
110 _iramend = .;
111 } > IRAM AT> DRAM
112
113 _iramcopy = LOADADDR(.iram);
114
115
116 .init ENDAUDIOADDR :
117 {
118 . = ALIGN(4);
119 _initstart = .;
120 *(.init*)
121 _initend = .;
122 } AT> DRAM
123
124 _initcopy = LOADADDR(.init);
125
126 .idle_stacks (NOLOAD) :
127 {
128 *(.idle_stacks)
129#if NUM_CORES > 1
130 cpu_idlestackbegin = .;
131 . += IDLE_STACK_SIZE;
132 cpu_idlestackend = .;
133#endif
134 cop_idlestackbegin = .;
135 . += IDLE_STACK_SIZE;
136 cop_idlestackend = .;
137 } > IRAM
138
139 .stack (NOLOAD) :
140 {
141 *(.stack)
142 stackbegin = .;
143 . += 0x2000;
144 stackend = .;
145 } > IRAM
146
147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss _noloaddram (NOLOAD) :
150 {
151 _edata = .;
152 *(.bss*)
153 *(COMMON)
154 . = ALIGN(0x4);
155 } > DRAM
156
157#if NOCACHE_BASE != 0
158 .ncbss . + NOCACHE_BASE (NOLOAD):
159 {
160 . = ALIGN(CACHEALIGN_SIZE);
161 *(.ncbss*)
162 . = ALIGN(CACHEALIGN_SIZE);
163 } AT> DRAM
164#endif
165
166 /* This will be aligned by preceding alignments */
167 .endaddr . - NOCACHE_BASE (NOLOAD) :
168 {
169 _end = .;
170 } > DRAM
171
172 .audiobuf (NOLOAD) :
173 {
174 _audiobuffer = .;
175 . = ALIGN(0x4);
176 audiobuffer = .;
177 } > DRAM
178
179 .audiobufend ENDAUDIOADDR (NOLOAD) :
180 {
181 audiobufend = .;
182 _audiobufend = .;
183 } > DRAM
184
185 .codec ENDAUDIOADDR (NOLOAD) :
186 {
187 codecbuf = .;
188 _codecbuf = .;
189 }
190
191 .plugin ENDADDR (NOLOAD) :
192 {
193 _pluginbuf = .;
194 pluginbuf = .;
195 }
196}
diff --git a/firmware/target/arm/philips/boot.lds b/firmware/target/arm/philips/boot.lds
index 45a9c6efa8..5a6fa000ad 100644
--- a/firmware/target/arm/philips/boot.lds
+++ b/firmware/target/arm/philips/boot.lds
@@ -3,69 +3,6 @@
3/* Can't link all Philips ARM devices the same way at this time */ 3/* Can't link all Philips ARM devices the same way at this time */
4#ifdef HAVE_BOOTLOADER_USB_MODE 4#ifdef HAVE_BOOTLOADER_USB_MODE
5#include "../pp/boot-pp502x-bl-usb.lds" 5#include "../pp/boot-pp502x-bl-usb.lds"
6#else /* !HAVE_BOOTLOADER_USB_MODE */ 6#else
7ENTRY(start) 7#include "../pp/boot-pp.lds"
8OUTPUT_FORMAT(elf32-littlearm)
9OUTPUT_ARCH(arm)
10STARTUP(target/arm/pp/crt0-pp-bl.o)
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000)
13
14#define DRAMORIG 0x10000000
15#ifndef IRAMORIG
16#define IRAMORIG 0x40000000
17#endif 8#endif
18#define IRAMSIZE 0x20000
19#define FLASHORIG 0x001f0000
20#define FLASHSIZE 2M
21
22MEMORY
23{
24 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
25 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
26}
27
28SECTIONS
29{
30 . = IRAMORIG;
31
32 .text : {
33 *(.init.text)
34 *(.text*)
35 *(.glue_7)
36 *(.glue_7t)
37 } > IRAM
38
39 .data : {
40 *(.icode)
41 *(.irodata)
42 *(.idata)
43 *(.data*)
44 *(.ncdata*)
45 *(.rodata*)
46 _dataend = . ;
47 } > IRAM
48
49 .stack (NOLOAD) : {
50 *(.stack)
51 _stackbegin = .;
52 stackbegin = .;
53 . += 0x2000;
54 _stackend = .;
55 stackend = .;
56 } > IRAM
57
58 /* The bss section is too large for IRAM - we just move it 16MB into the
59 DRAM */
60
61 . = DRAMORIG;
62 .bss . + (16*1024*1024) (NOLOAD) : {
63 _edata = .;
64 *(.bss*);
65 *(.ibss);
66 *(COMMON)
67 *(.ncbss*);
68 _end = .;
69 } > DRAM
70}
71#endif /* HAVE_BOOTLOADER_USB_MODE */
diff --git a/firmware/target/arm/pp/app-pp.lds b/firmware/target/arm/pp/app-pp.lds
new file mode 100644
index 0000000000..e6c2b255dd
--- /dev/null
+++ b/firmware/target/arm/pp/app-pp.lds
@@ -0,0 +1,199 @@
1/* Will have been included from app.lds */
2ENTRY(start)
3
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp.o)
7
8#define PLUGINSIZE PLUGIN_BUFFER_SIZE
9#define CODECSIZE CODEC_SIZE
10
11#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
12
13#define DRAMORIG 0x00000000
14#define IRAMORIG 0x40000000
15#define IRAMSIZE 0xc000
16
17#ifdef CPU_PP502x
18#define NOCACHE_BASE 0x10000000
19#else
20#define NOCACHE_BASE 0x28000000
21#endif
22
23#define CACHEALIGN_SIZE 16
24
25/* End of the audio buffer, where the codec buffer starts */
26#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
27
28/* Where the codec buffer ends, and the plugin buffer starts */
29#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
30
31MEMORY
32{
33 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
34 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
35}
36
37SECTIONS
38{
39 .text :
40 {
41 loadaddress = .;
42 _loadaddress = .;
43 . = ALIGN(0x200);
44 *(.init.text)
45 *(.text*)
46 *(.glue_7)
47 *(.glue_7t)
48 . = ALIGN(0x4);
49 } > DRAM
50
51 .rodata :
52 {
53 *(.rodata) /* problems without this, dunno why */
54 *(.rodata*)
55 *(.rodata.str1.1)
56 *(.rodata.str1.4)
57 . = ALIGN(0x4);
58 } > DRAM
59
60 .data :
61 {
62 *(.data*)
63 . = ALIGN(0x4);
64 } > DRAM
65
66#if NOCACHE_BASE != 0
67 /* .ncdata section is placed at uncached physical alias address and is
68 * loaded at the proper cached virtual address - no copying is
69 * performed in the init code */
70 .ncdata . + NOCACHE_BASE :
71 {
72 . = ALIGN(CACHEALIGN_SIZE);
73 *(.ncdata*)
74 . = ALIGN(CACHEALIGN_SIZE);
75 } AT> DRAM
76#endif
77
78 /DISCARD/ :
79 {
80 *(.eh_frame)
81 }
82
83 .vectors 0x0 :
84 {
85 _vectorsstart = .;
86 KEEP(*(.vectors));
87 _vectorsend = .;
88 } AT> DRAM
89
90 _vectorscopy = LOADADDR(.vectors);
91 _noloaddram = LOADADDR(.vectors);
92
93 .ibss IRAMORIG (NOLOAD) :
94 {
95 _iedata = .;
96 *(.qharray)
97 *(.ibss*)
98 . = ALIGN(0x4);
99 _iend = .;
100 } > IRAM
101
102 .iram _iend :
103 {
104 _iramstart = .;
105 *(.icode*)
106 *(.irodata*)
107 *(.idata*)
108 . = ALIGN(0x4);
109 _iramend = .;
110 } > IRAM AT> DRAM
111
112 _iramcopy = LOADADDR(.iram);
113
114
115 .init ENDAUDIOADDR :
116 {
117 . = ALIGN(4);
118 _initstart = .;
119 *(.init*)
120 _initend = .;
121 } AT> DRAM
122
123 _initcopy = LOADADDR(.init);
124
125 .idle_stacks (NOLOAD) :
126 {
127 *(.idle_stacks)
128#if NUM_CORES > 1
129 cpu_idlestackbegin = .;
130 . += IDLE_STACK_SIZE;
131 cpu_idlestackend = .;
132#endif
133 cop_idlestackbegin = .;
134 . += IDLE_STACK_SIZE;
135 cop_idlestackend = .;
136 } > IRAM
137
138 .stack (NOLOAD) :
139 {
140 *(.stack)
141 stackbegin = .;
142 . += 0x2000;
143 stackend = .;
144 } > IRAM
145
146 /* .bss and .ncbss are treated as a single section to use one init loop to
147 * zero it - note "_edata" and "_end" */
148 .bss _noloaddram (NOLOAD) :
149 {
150 _edata = .;
151 *(.bss*)
152 *(COMMON)
153 . = ALIGN(0x4);
154 } > DRAM
155
156#if NOCACHE_BASE != 0
157 .ncbss . + NOCACHE_BASE (NOLOAD):
158 {
159 . = ALIGN(CACHEALIGN_SIZE);
160 *(.ncbss*)
161 . = ALIGN(CACHEALIGN_SIZE);
162 } AT> DRAM
163#endif
164
165 /* This will be aligned by preceding alignments */
166 .endaddr . - NOCACHE_BASE (NOLOAD) :
167 {
168 _end = .;
169 } > DRAM
170
171 .audiobuf (NOLOAD) :
172 {
173 _audiobuffer = .;
174 . = ALIGN(0x4);
175 audiobuffer = .;
176 } > DRAM
177
178 .audiobufend ENDAUDIOADDR (NOLOAD) :
179 {
180#ifdef IPOD_VIDEO
181 audiobufend_lds = .;
182#else
183 audiobufend = .;
184#endif
185 _audiobufend = .;
186 } > DRAM
187
188 .codec ENDAUDIOADDR (NOLOAD) :
189 {
190 codecbuf = .;
191 _codecbuf = .;
192 }
193
194 .plugin ENDADDR (NOLOAD) :
195 {
196 _pluginbuf = .;
197 pluginbuf = .;
198 }
199}
diff --git a/firmware/target/arm/pp/boot-pp.lds b/firmware/target/arm/pp/boot-pp.lds
new file mode 100644
index 0000000000..602c3bf7ab
--- /dev/null
+++ b/firmware/target/arm/pp/boot-pp.lds
@@ -0,0 +1,92 @@
1#include "config.h"
2
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#if CONFIG_CPU == PP6100
11#define DRAMORIG 0x10f00000
12#ifndef IRAMORIG
13#define IRAMORIG 0x40000000
14#endif
15#define IRAMSIZE 0x20000
16#define FLASHORIG 0x001f0000
17#define FLASHSIZE 2M
18#if CONFIG_CPU == PP5020
19#define DRAMORIG 0x10000000
20#define IRAMORIG 0x40000000
21#define IRAMSIZE 0x18000
22#define FLASHORIG 0x001f0000
23#define FLASHSIZE 2M
24#elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
25#define DRAMORIG 0x10000000
26#ifndef IRAMORIG
27#define IRAMORIG 0x40000000
28#endif
29#define IRAMSIZE 0x20000
30#define FLASHORIG 0x001f0000
31#define FLASHSIZE 2M
32#elif CONFIG_CPU == PP5002
33#define DRAMORIG 0x28000000
34#define IRAMORIG 0x40000000
35#define IRAMSIZE 0x18000
36#define FLASHORIG 0x001f0000
37#define FLASHSIZE 2M
38#endif
39
40MEMORY
41{
42 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
43 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
44}
45
46SECTIONS
47{
48#ifdef SANSA_PP_ERASE
49 . = IRAMORIG+0x4000;
50#else
51 . = IRAMORIG;
52#endif
53
54 .text : {
55 *(.init.text)
56 *(.text*)
57 *(.glue_7)
58 *(.glue_7t)
59 } > IRAM
60
61 .data : {
62 *(.icode)
63 *(.irodata)
64 *(.idata)
65 *(.data*)
66 *(.ncdata*)
67 *(.rodata*)
68 _dataend = . ;
69 } > IRAM
70
71 .stack (NOLOAD) : {
72 *(.stack)
73 _stackbegin = .;
74 stackbegin = .;
75 . += 0x2000;
76 _stackend = .;
77 stackend = .;
78 } > IRAM
79
80 /* The bss section is too large for IRAM - we just move it 16MB into the
81 DRAM */
82
83 . = DRAMORIG;
84 .bss . + (16*1024*1024) (NOLOAD) : {
85 _edata = .;
86 *(.bss*);
87 *(.ibss);
88 *(COMMON)
89 *(.ncbss*);
90 _end = .;
91 } > DRAM
92}
diff --git a/firmware/target/arm/samsung/app.lds b/firmware/target/arm/samsung/app.lds
index 30e5962b82..856cc52bb0 100644
--- a/firmware/target/arm/samsung/app.lds
+++ b/firmware/target/arm/samsung/app.lds
@@ -1,196 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92 _noloaddram = LOADADDR(.vectors);
93
94 .ibss IRAMORIG (NOLOAD) :
95 {
96 _iedata = .;
97 *(.qharray)
98 *(.ibss)
99 . = ALIGN(0x4);
100 _iend = .;
101 } > IRAM
102
103 .iram _iend :
104 {
105 _iramstart = .;
106 *(.icode)
107 *(.irodata)
108 *(.idata)
109 . = ALIGN(0x4);
110 _iramend = .;
111 } > IRAM AT> DRAM
112
113 _iramcopy = LOADADDR(.iram);
114
115
116 .init ENDAUDIOADDR :
117 {
118 . = ALIGN(4);
119 _initstart = .;
120 *(.init*)
121 _initend = .;
122 } AT> DRAM
123
124 _initcopy = LOADADDR(.init);
125
126 .idle_stacks (NOLOAD) :
127 {
128 *(.idle_stacks)
129#if NUM_CORES > 1
130 cpu_idlestackbegin = .;
131 . += IDLE_STACK_SIZE;
132 cpu_idlestackend = .;
133#endif
134 cop_idlestackbegin = .;
135 . += IDLE_STACK_SIZE;
136 cop_idlestackend = .;
137 } > IRAM
138
139 .stack (NOLOAD) :
140 {
141 *(.stack)
142 stackbegin = .;
143 . += 0x2000;
144 stackend = .;
145 } > IRAM
146
147 /* .bss and .ncbss are treated as a single section to use one init loop to
148 * zero it - note "_edata" and "_end" */
149 .bss _noloaddram (NOLOAD) :
150 {
151 _edata = .;
152 *(.bss*)
153 *(COMMON)
154 . = ALIGN(0x4);
155 } > DRAM
156
157#if NOCACHE_BASE != 0
158 .ncbss . + NOCACHE_BASE (NOLOAD):
159 {
160 . = ALIGN(CACHEALIGN_SIZE);
161 *(.ncbss*)
162 . = ALIGN(CACHEALIGN_SIZE);
163 } AT> DRAM
164#endif
165
166 /* This will be aligned by preceding alignments */
167 .endaddr . - NOCACHE_BASE (NOLOAD) :
168 {
169 _end = .;
170 } > DRAM
171
172 .audiobuf (NOLOAD) :
173 {
174 _audiobuffer = .;
175 . = ALIGN(0x4);
176 audiobuffer = .;
177 } > DRAM
178
179 .audiobufend ENDAUDIOADDR (NOLOAD) :
180 {
181 audiobufend = .;
182 _audiobufend = .;
183 } > DRAM
184
185 .codec ENDAUDIOADDR (NOLOAD) :
186 {
187 codecbuf = .;
188 _codecbuf = .;
189 }
190
191 .plugin ENDADDR (NOLOAD) :
192 {
193 _pluginbuf = .;
194 pluginbuf = .;
195 }
196}
diff --git a/firmware/target/arm/samsung/boot.lds b/firmware/target/arm/samsung/boot.lds
index 9a42569aea..33b826bec8 100644
--- a/firmware/target/arm/samsung/boot.lds
+++ b/firmware/target/arm/samsung/boot.lds
@@ -1,64 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/boot-pp.lds"
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#define DRAMORIG 0x10000000
11#define IRAMORIG 0x40000000
12#define IRAMSIZE 0x18000
13#define FLASHORIG 0x001f0000
14#define FLASHSIZE 2M
15
16MEMORY
17{
18 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
19 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
20}
21
22SECTIONS
23{
24 . = IRAMORIG;
25
26 .text : {
27 *(.init.text)
28 *(.text*)
29 *(.glue_7)
30 *(.glue_7t)
31 } > IRAM
32
33 .data : {
34 *(.icode)
35 *(.irodata)
36 *(.idata)
37 *(.data*)
38 *(.ncdata*)
39 *(.rodata*)
40 _dataend = . ;
41 } > IRAM
42
43 .stack (NOLOAD) : {
44 *(.stack)
45 _stackbegin = .;
46 stackbegin = .;
47 . += 0x2000;
48 _stackend = .;
49 stackend = .;
50 } > IRAM
51
52 /* The bss section is too large for IRAM - we just move it 16MB into the
53 DRAM */
54
55 . = DRAMORIG;
56 .bss . + (16*1024*1024) (NOLOAD) : {
57 _edata = .;
58 *(.bss*);
59 *(.ibss);
60 *(COMMON)
61 *(.ncbss*);
62 _end = .;
63 } > DRAM
64}
diff --git a/firmware/target/arm/sandisk/app.lds b/firmware/target/arm/sandisk/app.lds
index a4b68ba994..856cc52bb0 100644
--- a/firmware/target/arm/sandisk/app.lds
+++ b/firmware/target/arm/sandisk/app.lds
@@ -1,193 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata*)
55 . = ALIGN(0x4);
56 } > DRAM
57
58 .data :
59 {
60 *(.data*)
61 . = ALIGN(0x4);
62 } > DRAM
63
64#if NOCACHE_BASE != 0
65 /* .ncdata section is placed at uncached physical alias address and is
66 * loaded at the proper cached virtual address - no copying is
67 * performed in the init code */
68 .ncdata . + NOCACHE_BASE :
69 {
70 . = ALIGN(CACHEALIGN_SIZE);
71 *(.ncdata*)
72 . = ALIGN(CACHEALIGN_SIZE);
73 } AT> DRAM
74#endif
75
76 /DISCARD/ :
77 {
78 *(.eh_frame)
79 }
80
81 .vectors 0x0 :
82 {
83 _vectorsstart = .;
84 KEEP(*(.vectors));
85 _vectorsend = .;
86 } AT> DRAM
87
88 _vectorscopy = LOADADDR(.vectors);
89 _noloaddram = LOADADDR(.vectors);
90
91 .ibss IRAMORIG (NOLOAD) :
92 {
93 _iedata = .;
94 *(.qharray)
95 *(.ibss*)
96 . = ALIGN(0x4);
97 _iend = .;
98 } > IRAM
99
100 .iram _iend :
101 {
102 _iramstart = .;
103 *(.icode*)
104 *(.irodata*)
105 *(.idata*)
106 . = ALIGN(0x4);
107 _iramend = .;
108 } > IRAM AT> DRAM
109
110 _iramcopy = LOADADDR(.iram);
111
112
113 .init ENDAUDIOADDR :
114 {
115 . = ALIGN(4);
116 _initstart = .;
117 *(.init*)
118 _initend = .;
119 } AT> DRAM
120
121 _initcopy = LOADADDR(.init);
122
123 .idle_stacks (NOLOAD) :
124 {
125 *(.idle_stacks)
126#if NUM_CORES > 1
127 cpu_idlestackbegin = .;
128 . += IDLE_STACK_SIZE;
129 cpu_idlestackend = .;
130#endif
131 cop_idlestackbegin = .;
132 . += IDLE_STACK_SIZE;
133 cop_idlestackend = .;
134 } > IRAM
135
136 .stack (NOLOAD) :
137 {
138 *(.stack)
139 stackbegin = .;
140 . += 0x2000;
141 stackend = .;
142 } > IRAM
143
144 /* .bss and .ncbss are treated as a single section to use one init loop to
145 * zero it - note "_edata" and "_end" */
146 .bss _noloaddram (NOLOAD) :
147 {
148 _edata = .;
149 *(.bss*)
150 *(COMMON)
151 . = ALIGN(0x4);
152 } > DRAM
153
154#if NOCACHE_BASE != 0
155 .ncbss . + NOCACHE_BASE (NOLOAD):
156 {
157 . = ALIGN(CACHEALIGN_SIZE);
158 *(.ncbss*)
159 . = ALIGN(CACHEALIGN_SIZE);
160 } AT> DRAM
161#endif
162
163 /* This will be aligned by preceding alignments */
164 .endaddr . - NOCACHE_BASE (NOLOAD) :
165 {
166 _end = .;
167 } > DRAM
168
169 .audiobuf (NOLOAD) :
170 {
171 _audiobuffer = .;
172 . = ALIGN(0x4);
173 audiobuffer = .;
174 } > DRAM
175
176 .audiobufend ENDAUDIOADDR (NOLOAD) :
177 {
178 audiobufend = .;
179 _audiobufend = .;
180 } > DRAM
181
182 .codec ENDAUDIOADDR (NOLOAD) :
183 {
184 codecbuf = .;
185 _codecbuf = .;
186 }
187
188 .plugin ENDADDR (NOLOAD) :
189 {
190 _pluginbuf = .;
191 pluginbuf = .;
192 }
193}
diff --git a/firmware/target/arm/sandisk/boot.lds b/firmware/target/arm/sandisk/boot.lds
index a4ea28ab8c..4586c09e20 100644
--- a/firmware/target/arm/sandisk/boot.lds
+++ b/firmware/target/arm/sandisk/boot.lds
@@ -3,79 +3,6 @@
3/* Can't link all Sansa PP devices the same way at this time */ 3/* Can't link all Sansa PP devices the same way at this time */
4#ifdef HAVE_BOOTLOADER_USB_MODE 4#ifdef HAVE_BOOTLOADER_USB_MODE
5#include "../pp/boot-pp502x-bl-usb.lds" 5#include "../pp/boot-pp502x-bl-usb.lds"
6#else /* !HAVE_BOOTLOADER_USB_MODE */
7
8ENTRY(start)
9OUTPUT_FORMAT(elf32-littlearm)
10OUTPUT_ARCH(arm)
11STARTUP(target/arm/pp/crt0-pp-bl.o)
12
13#define DRAMSIZE (MEMORYSIZE * 0x100000)
14
15#ifdef SANSA_VIEW
16#define DRAMORIG 0x10f00000
17#else
18#define DRAMORIG 0x10000000
19#endif
20
21#ifndef IRAMORIG
22#define IRAMORIG 0x40000000
23#endif
24#define IRAMSIZE 0x20000
25#define FLASHORIG 0x001f0000
26#define FLASHSIZE 2M
27
28MEMORY
29{
30 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
31 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
32}
33
34SECTIONS
35{
36#ifdef SANSA_PP_ERASE
37 . = IRAMORIG+0x4000;
38#else 6#else
39 . = IRAMORIG; 7#include "../pp/boot-pp.lds"
40#endif 8#endif \ No newline at end of file
41
42 .text : {
43 *(.init.text)
44 *(.text*)
45 *(.glue_7)
46 *(.glue_7t)
47 } > IRAM
48
49 .data : {
50 *(.icode)
51 *(.irodata)
52 *(.idata)
53 *(.data*)
54 *(.ncdata*)
55 *(.rodata*)
56 _dataend = . ;
57 } > IRAM
58
59 .stack (NOLOAD) : {
60 *(.stack)
61 _stackbegin = .;
62 stackbegin = .;
63 . += 0x2000;
64 _stackend = .;
65 stackend = .;
66 } > IRAM
67
68 /* The bss section is too large for IRAM - we just move it 16MB into the
69 DRAM */
70
71 . = DRAMORIG;
72 .bss . + (16*1024*1024) (NOLOAD) : {
73 _edata = .;
74 *(.bss*);
75 *(.ibss);
76 *(COMMON)
77 *(.ncbss*);
78 _end = .;
79 } > DRAM
80}
81#endif /* HAVE_BOOTLOADER_USB_MODE */
diff --git a/firmware/target/arm/tatung/app.lds b/firmware/target/arm/tatung/app.lds
index 4752e40ab7..856cc52bb0 100644
--- a/firmware/target/arm/tatung/app.lds
+++ b/firmware/target/arm/tatung/app.lds
@@ -1,184 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/app-pp.lds"
3ENTRY(start)
4
5OUTPUT_FORMAT(elf32-littlearm)
6OUTPUT_ARCH(arm)
7STARTUP(target/arm/pp/crt0-pp.o)
8
9#define PLUGINSIZE PLUGIN_BUFFER_SIZE
10#define CODECSIZE CODEC_SIZE
11
12#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - CODECSIZE
13
14#define DRAMORIG 0x00000000
15#define IRAMORIG 0x40000000
16#define IRAMSIZE 0xc000
17
18#ifdef CPU_PP502x
19#define NOCACHE_BASE 0x10000000
20#else
21#define NOCACHE_BASE 0x28000000
22#endif
23
24#define CACHEALIGN_SIZE 16
25
26/* End of the audio buffer, where the codec buffer starts */
27#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
28
29/* Where the codec buffer ends, and the plugin buffer starts */
30#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
31
32MEMORY
33{
34 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
35 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
36}
37
38SECTIONS
39{
40 .text :
41 {
42 loadaddress = .;
43 _loadaddress = .;
44 . = ALIGN(0x200);
45 *(.init.text)
46 *(.text*)
47 *(.glue_7)
48 *(.glue_7t)
49 . = ALIGN(0x4);
50 } > DRAM
51
52 .rodata :
53 {
54 *(.rodata) /* problems without this, dunno why */
55 *(.rodata*)
56 *(.rodata.str1.1)
57 *(.rodata.str1.4)
58 . = ALIGN(0x4);
59 } > DRAM
60
61 .data :
62 {
63 *(.data*)
64 . = ALIGN(0x4);
65 } > DRAM
66
67#if NOCACHE_BASE != 0
68 /* .ncdata section is placed at uncached physical alias address and is
69 * loaded at the proper cached virtual address - no copying is
70 * performed in the init code */
71 .ncdata . + NOCACHE_BASE :
72 {
73 . = ALIGN(CACHEALIGN_SIZE);
74 *(.ncdata*)
75 . = ALIGN(CACHEALIGN_SIZE);
76 } AT> DRAM
77#endif
78
79 /DISCARD/ :
80 {
81 *(.eh_frame)
82 }
83
84 .vectors 0x0 :
85 {
86 _vectorsstart = .;
87 KEEP(*(.vectors));
88 _vectorsend = .;
89 } AT> DRAM
90
91 _vectorscopy = LOADADDR(.vectors);
92
93 .ibss IRAMORIG (NOLOAD) :
94 {
95 _iedata = .;
96 *(.qharray)
97 *(.ibss)
98 . = ALIGN(0x4);
99 _iend = .;
100 } > IRAM
101
102 .iram _iend :
103 {
104 _iramstart = .;
105 *(.icode)
106 *(.irodata)
107 *(.idata)
108 . = ALIGN(0x4);
109 _iramend = .;
110 } > IRAM AT> DRAM
111
112 _iramcopy = LOADADDR(.iram);
113
114 .idle_stacks (NOLOAD) :
115 {
116 *(.idle_stacks)
117#if NUM_CORES > 1
118 cpu_idlestackbegin = .;
119 . += IDLE_STACK_SIZE;
120 cpu_idlestackend = .;
121#endif
122 cop_idlestackbegin = .;
123 . += IDLE_STACK_SIZE;
124 cop_idlestackend = .;
125 } > IRAM
126
127 .stack (NOLOAD) :
128 {
129 *(.stack)
130 stackbegin = .;
131 . += 0x2000;
132 stackend = .;
133 } > IRAM
134
135 /* .bss and .ncbss are treated as a single section to use one init loop to
136 * zero it - note "_edata" and "_end" */
137 .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.ncdata) +\
138 SIZEOF(.iram) + SIZEOF(.vectors) (NOLOAD) :
139 {
140 _edata = .;
141 *(.bss*)
142 *(COMMON)
143 . = ALIGN(0x4);
144 } > DRAM
145
146#if NOCACHE_BASE != 0
147 .ncbss . + NOCACHE_BASE (NOLOAD):
148 {
149 . = ALIGN(CACHEALIGN_SIZE);
150 *(.ncbss*)
151 . = ALIGN(CACHEALIGN_SIZE);
152 } AT> DRAM
153#endif
154
155 /* This will be aligned by preceding alignments */
156 .endaddr . - NOCACHE_BASE (NOLOAD) :
157 {
158 _end = .;
159 } > DRAM
160
161 .audiobuf (NOLOAD) :
162 {
163 _audiobuffer = .;
164 audiobuffer = .;
165 } > DRAM
166
167 .audiobufend ENDAUDIOADDR (NOLOAD) :
168 {
169 audiobufend = .;
170 _audiobufend = .;
171 } > DRAM
172
173 .codec ENDAUDIOADDR (NOLOAD) :
174 {
175 codecbuf = .;
176 _codecbuf = .;
177 }
178
179 .plugin ENDADDR (NOLOAD) :
180 {
181 _pluginbuf = .;
182 pluginbuf = .;
183 }
184}
diff --git a/firmware/target/arm/tatung/boot.lds b/firmware/target/arm/tatung/boot.lds
index 98d9cb62fe..33b826bec8 100644
--- a/firmware/target/arm/tatung/boot.lds
+++ b/firmware/target/arm/tatung/boot.lds
@@ -1,64 +1,2 @@
1#include "config.h" 1#include "config.h"
2 2#include "../pp/boot-pp.lds"
3ENTRY(start)
4OUTPUT_FORMAT(elf32-littlearm)
5OUTPUT_ARCH(arm)
6STARTUP(target/arm/pp/crt0-pp-bl.o)
7
8#define DRAMSIZE (MEMORYSIZE * 0x100000)
9
10#define DRAMORIG 0x10000000
11#define IRAMORIG 0x40000000
12#define IRAMSIZE 0x18000
13#define FLASHORIG 0x001f0000
14#define FLASHSIZE 2M
15
16MEMORY
17{
18 DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
19 IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
20}
21
22SECTIONS
23{
24 . = IRAMORIG;
25
26 .text : {
27 *(.init.text)
28 *(.text*)
29 *(.glue_7)
30 *(.glue_7t)
31 } > IRAM
32
33 .data : {
34 *(.icode)
35 *(.irodata)
36 *(.idata)
37 *(.data*)
38 *(.ncdata*)
39 *(.rodata*)
40 _dataend = . ;
41 } > IRAM
42
43 .stack (NOLOAD) : {
44 *(.stack)
45 _stackbegin = .;
46 stackbegin = .;
47 . += 0x2000;
48 _stackend = .;
49 stackend = .;
50 } > IRAM
51
52 /* The bss section is too large for IRAM - we just move it 16MB into the
53 DRAM */
54
55 . = DRAMORIG;
56 .bss . + (16*1024*1024) (NOLOAD) : {
57 _edata = .;
58 *(.bss*);
59 *(.ibss);
60 *(COMMON)
61 *(.ncbss*);
62 _end = .;
63 } > DRAM
64}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 14:23:01 +0000