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| author | Rafaël Carré <rafael.carre@gmail.com> | 2010-03-26 00:11:50 +0000 |
|---|---|---|
| committer | Rafaël Carré <rafael.carre@gmail.com> | 2010-03-26 00:11:50 +0000 |
| commit | b6065a8ceb83655d265c6c4adc4f30f7436e7bd7 (patch) | |
| tree | 1833e26e122f680aa235a0c210c3754d13c0f8ac /firmware/target/arm/system-target.h | |
| parent | e108d571ba6d74552f679c7251df4d0e85c5fd00 (diff) | |
| download | rockbox-b6065a8ceb83655d265c6c4adc4f30f7436e7bd7.tar.gz rockbox-b6065a8ceb83655d265c6c4adc4f30f7436e7bd7.zip | |
Use STORAGE_WANTS_ALIGN to make clear it's not a strict necessity
Define PROC_NEEDS_CACHEALIGN only for PP
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25339 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/system-target.h')
| -rw-r--r-- | firmware/target/arm/system-target.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 1422e6467a..157a450743 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
| @@ -164,7 +164,7 @@ static inline void wake_core(int core) | |||
| 164 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ | 164 | #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ |
| 165 | 165 | ||
| 166 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) | 166 | #if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) |
| 167 | #define NEEDS_STORAGE_ALIGN | 167 | #define STORAGE_WANTS_ALIGN |
| 168 | #endif | 168 | #endif |
| 169 | 169 | ||
| 170 | /** cache functions **/ | 170 | /** cache functions **/ |