PP5002: Clock setup cleanup. * Switch to 80MHz when boosted like on the other PP targets. * Prepare sleep mode by adding CPUFREQ_SLEEP. This is already confirmed working, but a lot of functions in rockbox will probably hang because the microsecond timer isn't running in this mode.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14096 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 40 insertions, 51 deletions

diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c
index 38dfe5b49c..5bff4fb202 100644
--- a/firmware/target/arm/system-pp5002.c
+++ b/firmware/target/arm/system-pp5002.c
@@ -91,60 +91,51 @@ static void ipod_init_cache(void)
     outl(0x3, 0xcf004024);
 }
     
-#endif
-
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 void set_cpu_frequency(long frequency)
+#else
+static void pp_set_cpu_frequency(long frequency)
+#endif
 {
-    unsigned long postmult;
-
-    if (CURRENT_CORE == CPU)
-    {
-        if (frequency == CPUFREQ_NORMAL)
-            postmult = CPUFREQ_NORMAL_MULT;
-        else if (frequency == CPUFREQ_MAX)
-            postmult = CPUFREQ_MAX_MULT;
-        else
-            postmult = CPUFREQ_DEFAULT_MULT;
-        cpu_frequency = frequency;
-
-        outl(0xd19b, 0xcf005038);
-
-        outl(inl(0xcf005010) | 0x6000, 0xcf005010);
-        outl(0x01, 0xcf005008);
-        outl(0xa9, 0xcf00500c);
-        outl(0xe000, 0xcf005010);
+    cpu_frequency = frequency;
 
-        /* Clock frequency = (24/4)*postmult */
-        outl(4, 0xcf005018);
-        outl(postmult, 0xcf00501c);
+    PLL_CONTROL |= 0x6000;     /* make sure some enable bits are set */
+    CLOCK_ENABLE = 0x01;       /* select source #1 */
 
-        /* Wait for PLL relock? */
-        udelay(200);
-
-        outl(0x02, 0xcf005008);
+    switch (frequency)
+    {
+      case CPUFREQ_MAX:
+        PLL_UNLOCK   = 0xd19b; /* unlock frequencies > 66MHz */
+        CLOCK_SOURCE = 0xa9;   /* source #1: 24 Mhz, source #2..#4: PLL */
+        PLL_CONTROL  = 0xe000; /* PLL enabled */
+        PLL_DIV      = 3;      /* 10/3 * 24MHz */
+        PLL_MULT     = 10;
+        udelay(200);           /* wait for relock */
+        break;
+
+      case CPUFREQ_NORMAL:
+        CLOCK_SOURCE = 0xa9;   /* source #1: 24 Mhz, source #2..#4: PLL */
+        PLL_CONTROL  = 0xe000; /* PLL enabled */
+        PLL_DIV      = 4;      /* 5/4 * 24MHz */
+        PLL_MULT     = 5;
+        udelay(200);           /* wait for relock */
+        break;
+        
+      case CPUFREQ_SLEEP:
+        CLOCK_SOURCE = 0x51;   /* source #2: 32kHz, #1, #2, #4: 24MHz */
+        PLL_CONTROL  = 0x6000; /* PLL disabled */
+        udelay(10000);         /* let 32kHz source stabilize? */
+        break;
+
+      default:
+        CLOCK_SOURCE = 0x55;   /* source #1..#4: 24 Mhz */
+        PLL_CONTROL  = 0x6000; /* PLL disabled */
+        cpu_frequency = CPUFREQ_DEFAULT;
+        break;
     }
+    CLOCK_ENABLE = 0x02;       /* select source #2 */
 }
-#elif !defined(BOOTLOADER)
-static void ipod_set_cpu_speed(void)
-{
-    outl(0xd19b, 0xcf005038);
-
-    outl(0x02, 0xcf005008);
-    outl(0x55, 0xcf00500c);
-    outl(0x6000, 0xcf005010);
-
-    /* 78  MHz (24*13/4) */
-    outl(4, 0xcf005018);
-    outl(13, 0xcf00501c);
-
-    outl(0xe000, 0xcf005010);
-
-    udelay(2000);
-
-    outl(0xa8, 0xcf00500c);
-}
-#endif
+#endif /* !BOOTLOADER */
 
 void system_init(void)
 {
@@ -165,7 +156,7 @@ void system_init(void)
         GPIOD_INT_EN   = 0;
 
 #ifndef HAVE_ADJUSTABLE_CPU_FREQ
-        ipod_set_cpu_speed();
+        pp_set_cpu_frequency(CPUFREQ_MAX);
 #endif
     }
     ipod_init_cache();
@@ -174,7 +165,7 @@ void system_init(void)
 
 void system_reboot(void)
 {
-    outl(inl(0xcf005030) | 0x4, 0xcf005030);
+    DEV_RS |= 4;
 }
 
 int system_memory_guard(int newmode)
@@ -182,5 +173,3 @@ int system_memory_guard(int newmode)
     (void)newmode;
     return 0;
 }
-
-