diff options
-rw-r--r-- | firmware/export/pp5002.h | 1 | ||||
-rw-r--r-- | firmware/target/arm/system-pp5002.c | 91 | ||||
-rw-r--r-- | firmware/target/arm/system-target.h | 12 |
3 files changed, 46 insertions, 58 deletions
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h index f2a7630ef6..082fc1c9cc 100644 --- a/firmware/export/pp5002.h +++ b/firmware/export/pp5002.h | |||
@@ -130,6 +130,7 @@ | |||
130 | #define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010)) | 130 | #define PLL_CONTROL (*(volatile unsigned long *)(0xcf005010)) |
131 | #define PLL_DIV (*(volatile unsigned long *)(0xcf005018)) | 131 | #define PLL_DIV (*(volatile unsigned long *)(0xcf005018)) |
132 | #define PLL_MULT (*(volatile unsigned long *)(0xcf00501c)) | 132 | #define PLL_MULT (*(volatile unsigned long *)(0xcf00501c)) |
133 | #define PLL_UNLOCK (*(volatile unsigned long *)(0xcf005038)) | ||
133 | 134 | ||
134 | #define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000)) | 135 | #define MMAP0_LOGICAL (*(volatile unsigned long *)(0xf000f000)) |
135 | #define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004)) | 136 | #define MMAP0_PHYSICAL (*(volatile unsigned long *)(0xf000f004)) |
diff --git a/firmware/target/arm/system-pp5002.c b/firmware/target/arm/system-pp5002.c index 38dfe5b49c..5bff4fb202 100644 --- a/firmware/target/arm/system-pp5002.c +++ b/firmware/target/arm/system-pp5002.c | |||
@@ -91,60 +91,51 @@ static void ipod_init_cache(void) | |||
91 | outl(0x3, 0xcf004024); | 91 | outl(0x3, 0xcf004024); |
92 | } | 92 | } |
93 | 93 | ||
94 | #endif | ||
95 | |||
96 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 94 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
97 | void set_cpu_frequency(long frequency) | 95 | void set_cpu_frequency(long frequency) |
96 | #else | ||
97 | static void pp_set_cpu_frequency(long frequency) | ||
98 | #endif | ||
98 | { | 99 | { |
99 | unsigned long postmult; | 100 | cpu_frequency = frequency; |
100 | |||
101 | if (CURRENT_CORE == CPU) | ||
102 | { | ||
103 | if (frequency == CPUFREQ_NORMAL) | ||
104 | postmult = CPUFREQ_NORMAL_MULT; | ||
105 | else if (frequency == CPUFREQ_MAX) | ||
106 | postmult = CPUFREQ_MAX_MULT; | ||
107 | else | ||
108 | postmult = CPUFREQ_DEFAULT_MULT; | ||
109 | cpu_frequency = frequency; | ||
110 | |||
111 | outl(0xd19b, 0xcf005038); | ||
112 | |||
113 | outl(inl(0xcf005010) | 0x6000, 0xcf005010); | ||
114 | outl(0x01, 0xcf005008); | ||
115 | outl(0xa9, 0xcf00500c); | ||
116 | outl(0xe000, 0xcf005010); | ||
117 | 101 | ||
118 | /* Clock frequency = (24/4)*postmult */ | 102 | PLL_CONTROL |= 0x6000; /* make sure some enable bits are set */ |
119 | outl(4, 0xcf005018); | 103 | CLOCK_ENABLE = 0x01; /* select source #1 */ |
120 | outl(postmult, 0xcf00501c); | ||
121 | 104 | ||
122 | /* Wait for PLL relock? */ | 105 | switch (frequency) |
123 | udelay(200); | 106 | { |
124 | 107 | case CPUFREQ_MAX: | |
125 | outl(0x02, 0xcf005008); | 108 | PLL_UNLOCK = 0xd19b; /* unlock frequencies > 66MHz */ |
109 | CLOCK_SOURCE = 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */ | ||
110 | PLL_CONTROL = 0xe000; /* PLL enabled */ | ||
111 | PLL_DIV = 3; /* 10/3 * 24MHz */ | ||
112 | PLL_MULT = 10; | ||
113 | udelay(200); /* wait for relock */ | ||
114 | break; | ||
115 | |||
116 | case CPUFREQ_NORMAL: | ||
117 | CLOCK_SOURCE = 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */ | ||
118 | PLL_CONTROL = 0xe000; /* PLL enabled */ | ||
119 | PLL_DIV = 4; /* 5/4 * 24MHz */ | ||
120 | PLL_MULT = 5; | ||
121 | udelay(200); /* wait for relock */ | ||
122 | break; | ||
123 | |||
124 | case CPUFREQ_SLEEP: | ||
125 | CLOCK_SOURCE = 0x51; /* source #2: 32kHz, #1, #2, #4: 24MHz */ | ||
126 | PLL_CONTROL = 0x6000; /* PLL disabled */ | ||
127 | udelay(10000); /* let 32kHz source stabilize? */ | ||
128 | break; | ||
129 | |||
130 | default: | ||
131 | CLOCK_SOURCE = 0x55; /* source #1..#4: 24 Mhz */ | ||
132 | PLL_CONTROL = 0x6000; /* PLL disabled */ | ||
133 | cpu_frequency = CPUFREQ_DEFAULT; | ||
134 | break; | ||
126 | } | 135 | } |
136 | CLOCK_ENABLE = 0x02; /* select source #2 */ | ||
127 | } | 137 | } |
128 | #elif !defined(BOOTLOADER) | 138 | #endif /* !BOOTLOADER */ |
129 | static void ipod_set_cpu_speed(void) | ||
130 | { | ||
131 | outl(0xd19b, 0xcf005038); | ||
132 | |||
133 | outl(0x02, 0xcf005008); | ||
134 | outl(0x55, 0xcf00500c); | ||
135 | outl(0x6000, 0xcf005010); | ||
136 | |||
137 | /* 78 MHz (24*13/4) */ | ||
138 | outl(4, 0xcf005018); | ||
139 | outl(13, 0xcf00501c); | ||
140 | |||
141 | outl(0xe000, 0xcf005010); | ||
142 | |||
143 | udelay(2000); | ||
144 | |||
145 | outl(0xa8, 0xcf00500c); | ||
146 | } | ||
147 | #endif | ||
148 | 139 | ||
149 | void system_init(void) | 140 | void system_init(void) |
150 | { | 141 | { |
@@ -165,7 +156,7 @@ void system_init(void) | |||
165 | GPIOD_INT_EN = 0; | 156 | GPIOD_INT_EN = 0; |
166 | 157 | ||
167 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | 158 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ |
168 | ipod_set_cpu_speed(); | 159 | pp_set_cpu_frequency(CPUFREQ_MAX); |
169 | #endif | 160 | #endif |
170 | } | 161 | } |
171 | ipod_init_cache(); | 162 | ipod_init_cache(); |
@@ -174,7 +165,7 @@ void system_init(void) | |||
174 | 165 | ||
175 | void system_reboot(void) | 166 | void system_reboot(void) |
176 | { | 167 | { |
177 | outl(inl(0xcf005030) | 0x4, 0xcf005030); | 168 | DEV_RS |= 4; |
178 | } | 169 | } |
179 | 170 | ||
180 | int system_memory_guard(int newmode) | 171 | int system_memory_guard(int newmode) |
@@ -182,5 +173,3 @@ int system_memory_guard(int newmode) | |||
182 | (void)newmode; | 173 | (void)newmode; |
183 | return 0; | 174 | return 0; |
184 | } | 175 | } |
185 | |||
186 | |||
diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 5c73f4ddd9..426d83f71a 100644 --- a/firmware/target/arm/system-target.h +++ b/firmware/target/arm/system-target.h | |||
@@ -26,17 +26,15 @@ | |||
26 | * moved into an appropriate subdir (or even split in 2). */ | 26 | * moved into an appropriate subdir (or even split in 2). */ |
27 | 27 | ||
28 | #if CONFIG_CPU == PP5002 | 28 | #if CONFIG_CPU == PP5002 |
29 | #define CPUFREQ_DEFAULT_MULT 4 | 29 | #define CPUFREQ_SLEEP 32768 |
30 | #define CPUFREQ_DEFAULT 24000000 | 30 | #define CPUFREQ_DEFAULT 24000000 |
31 | #define CPUFREQ_NORMAL_MULT 5 | 31 | #define CPUFREQ_NORMAL 30000000 |
32 | #define CPUFREQ_NORMAL 30000000 | 32 | #define CPUFREQ_MAX 80000000 |
33 | #define CPUFREQ_MAX_MULT 13 | ||
34 | #define CPUFREQ_MAX 78000000 | ||
35 | 33 | ||
36 | #else /* PP5022, PP5024 */ | 34 | #else /* PP5022, PP5024 */ |
37 | #define CPUFREQ_DEFAULT 24000000 | 35 | #define CPUFREQ_DEFAULT 24000000 |
38 | #define CPUFREQ_NORMAL 30000000 | 36 | #define CPUFREQ_NORMAL 30000000 |
39 | #define CPUFREQ_MAX 80000000 | 37 | #define CPUFREQ_MAX 80000000 |
40 | #endif | 38 | #endif |
41 | 39 | ||
42 | #define inl(a) (*(volatile unsigned long *) (a)) | 40 | #define inl(a) (*(volatile unsigned long *) (a)) |