Correct the memory sizes (IRAM and DRAM) for the Nano2G.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22025 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 42 insertions, 5 deletions

diff --git a/firmware/target/arm/s5l8700/pcm-s5l8700.c b/firmware/target/arm/s5l8700/pcm-s5l8700.c
index 7a4bdeb174..9421956131 100644
--- a/firmware/target/arm/s5l8700/pcm-s5l8700.c
+++ b/firmware/target/arm/s5l8700/pcm-s5l8700.c
@@ -48,7 +48,11 @@ static const struct div_entry {
     int             pdiv, mdiv, sdiv, cdiv;
 } div_table[HW_NUM_FREQ] = {
     [HW_FREQ_11] = {  26,  189,    3,    8},
+#ifdef IPOD_NANO2G
+    [HW_FREQ_22] = {  5,   6,    3,    4},
+#else
     [HW_FREQ_22] = {  50,   98,    2,    8},
+#endif
     [HW_FREQ_44] = {  37,  151,    1,    9},
     [HW_FREQ_88] = {  50,   98,    1,    4},
 #if 0   /* disabled because the codec driver does not support it (yet) */
@@ -116,6 +120,17 @@ void pcm_play_dma_start(const void *addr, size_t size)
                       DMA_IISOUT_DSIZE, DMA_IISOUT_BLEN, (void *)addr, size / 2,
                       dma_callback);
 
+#ifdef IPOD_NANO2G
+    I2STXCON = (0x10 << 16) |  /* burst length */
+               (0 << 15) |  /* 0 = falling edge */
+               (0 << 13) |  /* 0 = basic I2S format */
+               (0 << 12) |  /* 0 = MSB first */
+               (0 << 11) |  /* 0 = left channel for low polarity */
+               (5 << 8) |   /* MCLK divider */
+               (0 << 5) |   /* 0 = 16-bit */
+               (2 << 3) |   /* bit clock per frame */
+               (1 << 0);    /* channel index */
+#else
     /* S2: IIS Tx mode set */
     I2STXCON = (DMA_IISOUT_BLEN << 16) |  /* burst length */
                (0 << 15) |  /* 0 = falling edge */
@@ -126,6 +141,7 @@ void pcm_play_dma_start(const void *addr, size_t size)
                (0 << 5) |   /* 0 = 16-bit */
                (0 << 3) |   /* bit clock per frame */
                (1 << 0);    /* channel index */
+#endif
     
     /* S3: DMA channel 0 on */
     dma_enable_channel(DMA_IISOUT_CHANNEL);
@@ -169,7 +185,12 @@ void pcm_play_dma_pause(bool pause)
 void pcm_play_dma_init(void)
 {
     /* configure IIS pins */
+#ifdef IPOD_NANO2G
+    PCON5 = (PCON5 & ~(0xFFFFF000)) | 0x22220000;
+    PCON6 = (PCON6 & ~(0x0F000000)) | 0x02000000;
+#else
     PCON7 = (PCON7 & ~(0x0FFFFF00)) | 0x02222200;
+#endif
 
     /* enable clock to the IIS module */
     PWRCON &= ~(1 << 6);
@@ -185,26 +206,42 @@ void pcm_postinit(void)
 /* set the configured PCM frequency */
 void pcm_dma_apply_settings(void)
 {
-    audiohw_set_frequency(pcm_sampr);
+  //    audiohw_set_frequency(pcm_sampr);
     
     struct div_entry div = div_table[pcm_fsel];
-    
+
+    PLLCON &= ~4;
+    PLLCON &= ~0x10;
+    PLLCON &= 0x3f;
+    PLLCON |= 4;
+
     /* configure PLL1 and MCLK for the desired sample rate */
+#ifdef IPOD_NANO2G
+    PLL1PMS = (2 << 16) | /* PDIV */
+              (12 << 8) | /* MDIV */
+              (2 << 0);   /* SDIV */
+    PLL1LCNT = 0x4d2;
+#else
     PLL1PMS = (div.pdiv << 16) |
               (div.mdiv << 8) |
               (div.sdiv << 0);
     PLL1LCNT = 7500;    /* no idea what to put here */
-    
+#endif
+
     /* enable PLL1 and wait for lock */
     PLLCON |= (1 << 1);
     while ((PLLLOCK & (1 << 1)) == 0);
 
     /* configure MCLK */
-    CLKCON = (CLKCON & ~(0xFF)) |
+    CLKCON = (CLKCON & ~(0xFF)) | 
              (0 << 7) |         /* MCLK_MASK */
-             (2 << 5) |         /* MCLK_SEL = PLL1 */
+             (2 << 5) |         /* MCLK_SEL = PLL2 */
              (1 << 4) |         /* MCLK_DIV_ON */
+#ifdef IPOD_NANO2G
+             (3 - 1);           /* MCLK_DIV_VAL */
+#else
              (div.cdiv - 1);    /* MCLK_DIV_VAL */
+#endif
 }
 
 size_t pcm_get_bytes_waiting(void)