Beginning of an M:Robe 500i port. Currently only in the bootloader stage. Needs another piece of code to start the boot process - will be in the wiki.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@14763 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 39 insertions, 0 deletions

diff --git a/firmware/target/arm/olympus/mrobe-500/timer-target.h b/firmware/target/arm/olympus/mrobe-500/timer-target.h
new file mode 100644
index 0000000000..320b35d5d3
--- /dev/null
+++ b/firmware/target/arm/olympus/mrobe-500/timer-target.h
@@ -0,0 +1,39 @@
+/***************************************************************************
+*             __________               __   ___.
+*   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+*   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+*   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+*   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+*                     \/            \/     \/    \/            \/
+* $Id: $
+*
+* Copyright (C) 2007 by Karl Kurbjun
+*
+* All files in this archive are subject to the GNU General Public License.
+* See the file COPYING in the source tree root for full license agreement.
+*
+* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+* KIND, either express or implied.
+*
+****************************************************************************/
+#ifndef TIMER_TARGET_H
+#define TIMER_TARGET_H
+
+/* timer is based on PCLK and minimum division is 2 */
+#define TIMER_FREQ (49156800/2)
+
+bool __timer_set(long cycles, bool set);
+bool __timer_register(void);
+void __timer_unregister(void);
+
+#define __TIMER_SET(cycles, set) \
+    __timer_set(cycles, set)
+
+#define __TIMER_REGISTER(reg_prio, unregister_callback, cycles, \
+                              int_prio, timer_callback) \
+    __timer_register()
+
+#define __TIMER_UNREGISTER(...) \
+    __timer_unregister()
+
+#endif /* TIMER_TARGET_H */