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author | Michael Sevakis <jethead71@rockbox.org> | 2011-10-17 15:37:14 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2011-10-17 15:37:14 +0000 |
commit | feddfdb2d9e56c132d91d72b6c7a595fa0b83a16 (patch) | |
tree | 52eb3cf18e5cdde0ffa1c06c85668332e9649631 /firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c | |
parent | 2a478c826bff003a46a35c4cff2ca961c208c38f (diff) | |
download | rockbox-feddfdb2d9e56c132d91d72b6c7a595fa0b83a16.tar.gz rockbox-feddfdb2d9e56c132d91d72b6c7a595fa0b83a16.zip |
Gigabeat S/i.MX31/wm8978: Clean up clocking information in the general wmcodec/pcm drivers and move it to the target's wmcodec/i2s files.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30771 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c')
-rw-r--r-- | firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c | 83 |
1 files changed, 76 insertions, 7 deletions
diff --git a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c index 36ab33a5dc..ca23aa4e56 100644 --- a/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/wmcodec-gigabeat-s.c | |||
@@ -22,24 +22,93 @@ | |||
22 | ****************************************************************************/ | 22 | ****************************************************************************/ |
23 | #include "config.h" | 23 | #include "config.h" |
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include "kernel.h" | 25 | #include "audiohw.h" |
26 | #include "sound.h" | ||
27 | #include "wmcodec.h" | 26 | #include "wmcodec.h" |
27 | #include "audio.h" | ||
28 | #include "i2s.h" | 28 | #include "i2s.h" |
29 | #include "i2c-imx31.h" | 29 | #include "i2c-imx31.h" |
30 | 30 | ||
31 | /* NOTE: Some port-specific bits will have to be moved away (node and GPIO | ||
32 | * writes) for cleanest implementation. */ | ||
33 | |||
34 | static struct i2c_node wm8978_i2c_node = | 31 | static struct i2c_node wm8978_i2c_node = |
35 | { | 32 | { |
36 | .num = I2C1_NUM, | 33 | .num = I2C1_NUM, |
37 | .ifdr = I2C_IFDR_DIV192, /* 66MHz/.4MHz = 165, closest = 192 = 343750Hz */ | 34 | .ifdr = I2C_IFDR_DIV192, /* 66MHz/.4MHz = 165, closest = 192 = 343750Hz */ |
38 | /* Just hard-code for now - scaling may require | ||
39 | * updating */ | ||
40 | .addr = WMC_I2C_ADDR, | 35 | .addr = WMC_I2C_ADDR, |
41 | }; | 36 | }; |
42 | 37 | ||
38 | /* For 16.9344MHz MCLK, codec as master. */ | ||
39 | const struct wmc_srctrl_entry wmc_srctrl_table[HW_NUM_FREQ] = | ||
40 | { | ||
41 | [HW_FREQ_8] = /* PLL = 65.536MHz */ | ||
42 | { | ||
43 | .plln = 7 | WMC_PLL_PRESCALE, | ||
44 | .pllk1 = 0x2f, /* 12414886 */ | ||
45 | .pllk2 = 0x0b7, | ||
46 | .pllk3 = 0x1a6, | ||
47 | .mclkdiv = WMC_MCLKDIV_8, /* 2.0480 MHz */ | ||
48 | .filter = WMC_SR_8KHZ, | ||
49 | }, | ||
50 | [HW_FREQ_11] = /* PLL = off */ | ||
51 | { | ||
52 | .mclkdiv = WMC_MCLKDIV_6, /* 2.8224 MHz */ | ||
53 | .filter = WMC_SR_12KHZ, | ||
54 | }, | ||
55 | [HW_FREQ_12] = /* PLL = 73.728 MHz */ | ||
56 | { | ||
57 | .plln = 8 | WMC_PLL_PRESCALE, | ||
58 | .pllk1 = 0x2d, /* 11869595 */ | ||
59 | .pllk2 = 0x08e, | ||
60 | .pllk3 = 0x19b, | ||
61 | .mclkdiv = WMC_MCLKDIV_6, /* 3.0720 MHz */ | ||
62 | .filter = WMC_SR_12KHZ, | ||
63 | }, | ||
64 | [HW_FREQ_16] = /* PLL = 65.536MHz */ | ||
65 | { | ||
66 | .plln = 7 | WMC_PLL_PRESCALE, | ||
67 | .pllk1 = 0x2f, /* 12414886 */ | ||
68 | .pllk2 = 0x0b7, | ||
69 | .pllk3 = 0x1a6, | ||
70 | .mclkdiv = WMC_MCLKDIV_4, /* 4.0960 MHz */ | ||
71 | .filter = WMC_SR_16KHZ, | ||
72 | }, | ||
73 | [HW_FREQ_22] = /* PLL = off */ | ||
74 | { | ||
75 | .mclkdiv = WMC_MCLKDIV_3, /* 5.6448 MHz */ | ||
76 | .filter = WMC_SR_24KHZ, | ||
77 | }, | ||
78 | [HW_FREQ_24] = /* PLL = 73.728 MHz */ | ||
79 | { | ||
80 | .plln = 8 | WMC_PLL_PRESCALE, | ||
81 | .pllk1 = 0x2d, /* 11869595 */ | ||
82 | .pllk2 = 0x08e, | ||
83 | .pllk3 = 0x19b, | ||
84 | .mclkdiv = WMC_MCLKDIV_3, /* 6.1440 MHz */ | ||
85 | .filter = WMC_SR_24KHZ, | ||
86 | }, | ||
87 | [HW_FREQ_32] = /* PLL = 65.536MHz */ | ||
88 | { | ||
89 | .plln = 7 | WMC_PLL_PRESCALE, | ||
90 | .pllk1 = 0x2f, /* 12414886 */ | ||
91 | .pllk2 = 0x0b7, | ||
92 | .pllk3 = 0x1a6, | ||
93 | .mclkdiv = WMC_MCLKDIV_2, /* 8.1920 MHz */ | ||
94 | .filter = WMC_SR_32KHZ, | ||
95 | }, | ||
96 | [HW_FREQ_44] = /* PLL = off */ | ||
97 | { | ||
98 | .mclkdiv = WMC_MCLKDIV_1_5, /* 11.2896 MHz */ | ||
99 | .filter = WMC_SR_48KHZ, | ||
100 | }, | ||
101 | [HW_FREQ_48] = /* PLL = 73.728 MHz */ | ||
102 | { | ||
103 | .plln = 8 | WMC_PLL_PRESCALE, | ||
104 | .pllk1 = 0x2d, /* 11869595 */ | ||
105 | .pllk2 = 0x08e, | ||
106 | .pllk3 = 0x19b, | ||
107 | .mclkdiv = WMC_MCLKDIV_1_5, /* 12.2880 MHz */ | ||
108 | .filter = WMC_SR_48KHZ, | ||
109 | }, | ||
110 | }; | ||
111 | |||
43 | void audiohw_init(void) | 112 | void audiohw_init(void) |
44 | { | 113 | { |
45 | i2s_reset(); | 114 | i2s_reset(); |